Verilog/dump.vcd at main · dice-apps/Verilog · GitHub

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$date
	Sun Jun 01 22:39:54 2025
$end
$version
	Icarus Verilog
$end
$timescale
	1ps
$end
$scope module tb $end
$var wire 8 ! data_out [7:0] $end
$var reg 1 " clk $end
$var reg 8 # data_in [7:0] $end
$var reg 1 $ load $end
$var reg 1 % reset $end
$scope module uut $end
$var wire 1 " clk $end
$var wire 8 & data_in [7:0] $end
$var wire 1 $ load $end
$var wire 1 % reset $end
$var reg 8 ' data_out [7:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b0 '
b0 &
1%
0$
b0 #
0"
b0 !
$end
#5000
1"
#10000
0"
#15000
1"
#20000
0"
0%
#25000
1"
#30000
0"
1$
b10101010 #
b10101010 &
#35000
b10101010 !
b10101010 '
1"
#40000
0"
0$
#45000
1"
#50000
0"
#55000
1"
#60000
0"
1$
b1010101 #
b1010101 &
#65000
b1010101 !
b1010101 '
1"
#70000
0"
0$
#75000
1"
#80000
0"
#85000
1"
#90000
0"
b11111111 #
b11111111 &
#95000
1"
#100000
0"
#105000
1"
#110000
0"
#115000
1"
#120000
0"
#125000
1"
#130000
0"
#135000
1"
#140000
0"