write V with helix #2837
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the-mikedavis
cooperspencer
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Hi, Can anyone help me out? |
Answered by
the-mikedavis
Jun 20, 2022
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V and Verilog clash because they both use the |
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V and Verilog clash because they both use the
.vextension for files. To force V, you can remove thevextension from Verilog's configuration: #2526 (comment)