🇬🇷 Ελληνική έκδοση: README_GR.md
This repository contains my laboratory work for the course Introduction to VLSI, focusing on CMOS digital circuit design, simulation, and physical verification.
All designs were implemented using Cadence Virtuoso following a full custom VLSI design flow.
- EDA Tool: Cadence Virtuoso
- Simulation Environment: Cadence Virtuoso (transient and DC analysis)
- Design Flow: Schematic → Symbol → Layout → DRC → LVS → Simulation
- Design and sizing of a CMOS inverter
- Schematic, symbol, and layout creation
- Transient simulation and delay extraction
- Study of transistor sizing effects on performance
- Design of 2-input NAND and NOR gates
- Full schematic and layout implementation
- Functional verification through simulation
- Timing analysis
- Circuit with three inverters sharing a common input
- Different transistor sizing per inverter
- Study of propagation delay and load capacitance
- Transient and DC analysis
- Design Rule Check (DRC)
- Layout Versus Schematic (LVS)
- Verification of all previously designed circuits
- Implementation of a composite Boolean function
- Full CMOS realization
- Performance analysis under different output loads
- DC and transient simulations
- Design of XOR, Half Adder, and Full Adder blocks
- Use of standard-cell D Flip-Flops
- Construction of a 4-bit serial adder
- Timing and carry propagation analysis
This repository documents my hands-on experience with:
- CMOS digital circuit design
- Transistor-level logic implementation
- Timing and performance analysis
- Physical verification (DRC/LVS)
- Sequential logic in VLSI systems
This repository contains personal academic laboratory work. Shared for educational and reference purposes only.
All Rights Reserved.