Popular repositories Loading

1. Internship-VNX-_PMIC_LDO Internship-VNX-_PMIC_LDO Public

   Documentation and performance reports for an ultra-low-power dual-loop LDO of PMIC designed during my internship.

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2. 9-bit-SAR-ADC 9-bit-SAR-ADC Public

   Full custom IC design, layout, and post-layout verification of a 9-bit differential Successive Approximation Register (SAR) ADC in TSMC 65nm. Taped out as part of a 7-group collaborative top chip.

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3. Two-Stage-Folded-Cascode-OTA Two-Stage-Folded-Cascode-OTA Public

   Transistor-level design of a low-power (1.18mW) Two-Stage Folded-Cascode OTA in 0.18µm CMOS. Optimized for high DC gain and bandwidth utilizing the systematic gm/ID sizing methodology.

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4. ECG-Amplifier-Employing-Driven-Right-Leg-Feedback ECG-Amplifier-Employing-Driven-Right-Leg-Feedback Public

   A 2.7μW, 127dB CMRR 3-OpAmp Instrumentation Amplifier with Driven-Right-Leg feedback for wearable biopotential monitoring in 180nm CMOS.

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5. Zero-IF-Receiver Zero-IF-Receiver Public

   A full-custom 2.1–2.7 GHz Direct-Conversion (Zero-IF) Receiver Front-End designed in TSMC 65nm CMOS. This repository details the schematic design and SpectreRF verification of a PVT-invariant casco…

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6. Gate-Driver-Circuit-Design-and-PCB-Layout-Optimization-for-SiC-MOSFET Gate-Driver-Circuit-Design-and-PCB-Layout-Optimization-for-SiC-MOSFET Public

   Hardware implementation of a Double Pulse Test (DPT) platform for SiC MOSFETs. Features LTspice parasitic modeling, ANSYS Q3D extraction, and a novel 4-layer Vertical Multi-Loop PCB layout that min…

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