A curated map of the modern semiconductor industry, with a deliberate bias toward the two places where the hardest engineering now happens: logic below 10 nm and inside the package.
Most "awesome semiconductor" lists are really awesome-RTL lists — they stop at the GDSII handoff. This one starts there and keeps going: how the pattern actually gets onto silicon (EUV, High-NA, computational lithography, OPC and ILT), how atoms get added and removed (deposition, etch, CMP, implant, epitaxy), how the die gets measured, thinned, bonded, stacked, and cooled (metrology and yield, TSVs, hybrid bonding, 2.5D interposers, fan-out and panel-level packaging, chiplets and die-to-die interfaces), and how the factory that does all of it is scheduled and financed.
Everything here is a link to something you can read, run, download, or attend. Where a topic is dominated by proprietary tools, the list says so rather than pretending an open-source equivalent exists.
Scope
- ✅ Advanced logic scaling (FinFET → GAA nanosheet → forksheet → CFET, backside power delivery), lithography, process modules, metrology, memory (DRAM, 3D NAND, HBM), advanced packaging and chiplets, TCAD, EDA for 3D, fab operations, test, reliability, and the economics/policy layer around all of it.
- ✅ Open-source tools, public datasets, benchmark suites, standards, roadmaps, and papers.
⚠️ Not a startup database — for that see awesome-semiconductor-startups.⚠️ Not an RTL/HDL list — for that see awesome-opensource-hardware.
A note on node names. "3 nm", "2 nm", "A16", "18A" are marketing names, not physical dimensions. Nothing in a modern logic node measures the number in its name. When precision matters this list uses the physical parameters that actually scale: contacted poly pitch (CPP), metal pitch (MP), cell height in tracks, and fin/sheet count.
- 1. Start Here
- 2. Roadmaps and Standards Bodies
- 3. Advanced Logic Scaling
- 4. Lithography and Patterning
- 5. Process Modules, Materials and Equipment
- 6. Metrology, Inspection and Yield
- 7. Memory Technology
- 8. Advanced Packaging
- 9. Chiplets and Die-to-Die Interfaces
- 10. Design and EDA for Advanced Nodes and 3D
- 11. TCAD and Physical Simulation
- 12. AI and Machine Learning for Semiconductors
- 13. Fab Operations and Manufacturing Science
- 14. Test, Reliability and Hardware Security
- 15. Economics, Markets and Policy
- 16. Learning Resources
- 17. Conferences, Journals and Communities
- 18. Research Institutes and Consortia
- 19. Industry Map
- 20. DIY and Garage Fab
- 21. Related Awesome Lists
If you are new to the field, read in this order. Each of these is free and gives you the vocabulary for everything below.
- IRDS — International Roadmap for Devices and Systems - The successor to the ITRS. Free PDF chapters covering More Moore, Beyond CMOS, Lithography, Metrology, Packaging Integration, and Systems and Architectures. The single best free orientation to where the industry thinks it is going.
- Heterogeneous Integration Roadmap (HIR) - IEEE EPS 20+ chapter roadmap dedicated entirely to packaging and integration. Free download, updated on a rolling basis.
- Semiconductor Engineering Knowledge Center - Encyclopedia-style entries for essentially every term in this list, each linked to the news articles that use it.
- imec Technology Articles - The research institute that most of the industry co-funds, explaining its own results in plain language. Best free source on CFET, backside power, semi-damascene, and 2D materials.
- Asianometry — Semiconductor playlist - Long-form video explainers on fab history, equipment, and geopolitics. Unusually well-sourced.
- Construction Physics — Semiconductor fab reading list - An annotated reading list for understanding fabs as physical, capital-intensive factories.
- Chips and Cheese - Independent microarchitecture and silicon analysis. The best free source on what shipping chips actually do, as opposed to what their datasheets claim.
- TechInsights - Reverse-engineering firm whose public blog posts frequently reveal actual as-built dimensions of shipping nodes.
How to read a node. The parameters that matter, in rough order of importance: contacted poly pitch (CPP / gate pitch), minimum metal pitch (MMP / M0 pitch), standard cell height in metal tracks, number of fins or sheets per device, SRAM bit-cell area, and whether power is delivered front-side or backside. Everything else is marketing.
- IRDS 2023/2025 Editions - Free, chapter-by-chapter. Start with More Moore and Lithography.
- Heterogeneous Integration Roadmap - Chapters on Single-Chip and Multi-Chip Integration, 2.5D/3D, Interconnects for 2D/3D, Thermal, Test, Reliability, Co-Design, and Photonics.
- SEMI — Heterogeneous Integration Roadmap community - SEMI's landing page for HIR participation.
- ITRS Archive (2.0, 2015) - The historical roadmap. Still worth reading for how the industry framed scaling before the "equivalent scaling" era.
- OCP Open Domain-Specific Architecture (ODSA) - Open Compute Project workstream that produced Bunch of Wires and much of the early open chiplet ecosystem work.
- SEMI Standards - The ~1,000-document body governing wafer dimensions, equipment communication (E30/E37/E5), carrier and FOUP interfaces (E47), facilities, safety (S2/S8), and traceability. Individual standards are paid; the index and scope statements are free.
- JEDEC - Memory and packaging standards: DDR5, LPDDR6, HBM (JESD270 series), package outlines (JEP/MO), and reliability test methods (JESD22, JESD47, JEP122 for failure mechanisms). Free registration to download.
- IPC - Substrate, board, and assembly standards; increasingly relevant as packaging substrates become the bottleneck.
- IEEE Standards Association — Electronics Packaging - Home of IEEE 1838 (3D test access), 1687 (IJTAG), 1149.1 (JTAG), 2851, and the P3405 chiplet family.
- Open Compute Project - Where hyperscaler-driven packaging, chiplet, and co-packaged-optics requirements get published before they become products.
- UCIe Consortium - Universal Chiplet Interconnect Express specification and compliance program.
- Optical Internetworking Forum (OIF) - Electrical and optical interface implementation agreements (CEI-112G/224G, co-packaged optics frameworks).
- Si2 (Silicon Integration Initiative) - OpenAccess, OpenPDK, and the Compact Model Coalition (BSIM-CMG for FinFET/GAA).
- Compact Model Coalition — BSIM Group - BSIM-CMG is the industry standard compact model for FinFET and gate-all-around devices. Source code is downloadable.
Everything in this section is about the front end of line and middle of line at pitches where single-exposure patterning has run out and electrostatics no longer come for free.
- TSMC Technology Roadmap - Official N7 / N5 / N3 / N2 / A16 / A14 descriptions. A16 introduces Super Power Rail (TSMC's backside power delivery); A14 is the first TSMC node targeted at High-NA.
- Intel Foundry Process Technology - Intel 7 / 4 / 3 / 18A / 14A. Intel 18A pairs RibbonFET (GAA) with PowerVia (backside power) and was the first node to ship with backside power delivery in volume.
- Samsung Foundry Process - SF4 / SF3 / SF2 / SF1.4. Samsung was first to production with GAA (MBCFET) at 3 nm.
- Rapidus - Japan's 2 nm greenfield effort with IBM and imec; notable for a single-wafer, no-batch, fully-AI-scheduled fab concept.
- Wikipedia — 2 nm and 3 nm process - Unglamorous but well-sourced cross-foundry tables of announced CPP, metal pitch, and density, with citations back to the original IEDM and press disclosures.
- SemiAnalysis — foundry process deep dives - Paid, but the free posts are the most detailed public accounting of node economics and wafer pricing.
- imec — CFET (complementary FET) - The architecture that stacks an nFET directly on a pFET. imec targets monolithic CFET around the A7 node, with monolithic and sequential integration flows differing sharply in thermal budget.
- imec — Outer wall forksheet - The bridge device between nanosheet and CFET, intended to extend the nanosheet roadmap to roughly the A10 node with easier fabrication than the inner-wall forksheet.
- imec — Scaling monolithic CFET across multiple nodes - What has to be true (channel stress, contact resistance, middle dielectric isolation) for CFET to scale rather than merely exist.
- Intel RibbonFET - Intel's gate-all-around implementation.
- Samsung MBCFET - Multi-Bridge Channel FET, the first GAA device in high-volume manufacturing.
- EE Times — VLSI 2025: Outer Wall Forksheet - Readable conference coverage of the forksheet/CFET transition.
- Semiconductor Digest — Performance boosters for monolithic CFET - Companion write-up with the device-level numbers.
- Nanosheet vs FinFET — Semiconductor Engineering - Knowledge-center entry with links to a decade of GAA coverage.
Key primary sources. The device papers themselves land at three venues every year: IEDM (December), the VLSI Symposium (June), and ECS/ECS Transactions for the materials and process chemistry side. IEDM short courses are the single densest tutorial material in the industry.
Moving the power distribution network to the wafer backside frees front-side routing tracks for signals, cuts IR drop, and decouples power and signal RC. It also requires extreme wafer thinning, carrier bonding, and nano-TSVs in every standard cell — which is why it arrived with 18A/A16 and not earlier.
- imec — How to power chips from the backside - The clearest free explanation of nano-TSV and buried power rail (BPR) flows.
- imec — DTCO study of backside power delivery options - imec/Arm co-optimization comparing BPR-based and nTSV-only implementations.
- Intel — PowerVia - Intel reports 5–10% standard cell utilization improvement and up to ~4% ISO-power performance gain from decoupling power and signal routing.
- TrendForce — Clearwater Forest 18A backside power at Hot Chips - Where PowerVia and TSMC Super Power Rail stand relative to each other.
- Tom's Hardware — PowerVia technical detail - Good coverage of the test-vehicle results Intel published before productizing.
- Semiconductor Engineering — Big changes in power delivery, materials, and interconnects - Ties backside power to the interconnect metallization change happening at the same time.
Below roughly 20 nm metal pitch, copper's effective resistivity blows up because barrier and liner thickness stop scaling and surface/grain-boundary scattering dominates. The industry's answers are barrier-less metals (Ru, Mo), subtractive patterning, and airgaps.
- imec — 16 nm pitch Ru lines by semi-damascene - Record-low line resistance at 16 nm pitch using a subtractive/semi-damascene flow.
- imec — Semi-damascene with fully self-aligned vias at 18 nm metal pitch - Fully self-aligned vias are what makes semi-damascene manufacturable.
- Subtractive Ruthenium Interconnects with Airgap (IEEE) - The airgap integration that turns Ru's resistance advantage into an actual capacitance win.
- IITC — International Interconnect Technology Conference - The interconnect venue. Past programs are public and are the best index of what is being tried: 2025 program, 2024 program.
- Semiconductor Engineering — Interconnects approach tipping point - Survey of the Cu → Ru/Mo transition and why it is happening now.
- Spatially resolved conductivity of rectangular interconnects (arXiv) - Physical modeling of surface scattering; useful if you want to compute rather than cite.
Design-technology co-optimization is now where most of the "node" improvement comes from. Cell height reduction, fin/sheet depopulation, buried rails, and via-pillar schemes deliver density that lithography alone no longer does.
- imec — Design-technology co-optimization - imec's DTCO program pages, including the standard-cell architectures used in their public studies.
- Si2 OpenPDK / OpenAccess - Database standard underneath most commercial physical design tools.
- ASAP7 Predictive PDK - Arizona State / ARM 7 nm predictive PDK built on realistic EUV-era ground rules. The standard academic vehicle for sub-10 nm physical design research.
- ASAP7 on GitHub - Packaged for use with open-source flows.
- FreePDK15 - NCSU's 15 nm FinFET predictive kit.
- BSIM-CMG - Berkeley's common multi-gate compact model, the industry standard for FinFET and nanosheet SPICE models. Source available.
- Semiconductor Engineering — System-technology co-optimization (STCO) - Where DTCO stops and packaging-aware STCO begins.
- imec/ASML/TSMC — 300 mm 2D-material CMOS at 50 nm CPP - MoS₂ nFETs and WS₂/WSe₂ pFETs on the same 300 mm wafer at 50 nm contacted poly pitch, with 94% of transistors operational. The most significant lab-to-fab step 2D materials have taken.
- imec — 2D-material devices in the logic scaling roadmap - Where 2D channels plausibly enter: ultra-scaled logic, but also backend and wafer-backside devices.
- Semiconductor Today — 300 mm integration route for 2D FETs - Process-flow-level summary.
- IRDS Beyond CMOS chapter - Systematic comparison of tunnel FETs, spin devices, ferroelectric logic, and 2D materials against CMOS baselines.
- Nature Electronics — 2D semiconductors collection - Primary literature aggregation.
- Stanford SystemX / N3XT - Carbon nanotube FETs, RRAM, and monolithic 3D as a system-level alternative to conventional scaling.
- ASML — EUV lithography systems - Product pages for the NXE 0.33 NA platform, including throughput and overlay specifications.
- ASML — Technology explained - Vendor-authored but genuinely good tutorials on how the source, optics, reticle stage, and wafer stage work together.
- IRDS Lithography chapter - Vendor-neutral resolution, overlay, and CD-uniformity requirements per node, with the multi-patterning decision tree.
- SPIE Advanced Lithography + Patterning - The conference where every EUV result is first published. Proceedings are paywalled; abstracts and program are free and are a useful index.
- Chris Mack — Lithography resources - Decades of free lecture notes, the Field Guide to Optical Lithography, and the definitive plain-English writing on resolution, DOF, and stochastic effects.
- Lithography basics — Semiconductor Engineering - Aggregated coverage with the EUV/DUV/multi-patterning terminology defined.
0.55 NA anamorphic optics buy roughly 8 nm single-exposure resolution — a step that avoids EUV double patterning at the tightest pitches — at the cost of a half-field (26 × 16.5 mm) exposure, which forces field stitching for large dies.
- ASML — EXE:5000 / High-NA EUV - Specifications for the first-generation High-NA platform.
- Intel — High-NA EUV in the foundry - Intel's account of installing and qualifying the first commercial High-NA tools.
- Tom's Hardware — First commercial EXE:5200B installation - Where High-NA sits relative to Intel 14A.
- Tom's Hardware — ASML lithography roadmap from DUV to Hyper-NA - The full scanner roadmap in one place, including what Hyper-NA (>0.55) would require.
- Anamorphic imaging and field stitching - Mack's essays on why anamorphic optics halve the field and what that costs designers.
Design consequence worth internalizing: a half-field High-NA reticle means reticle-limited die area drops to roughly 429 mm². This is one of the strongest structural forces pushing large designs toward chiplets — see section 9.
- EUV source technology — laser-produced plasma - Tin droplets, pre-pulse/main-pulse CO₂ lasers, collector mirror lifetime, and why source power is the throughput limiter.
- Photomask technology at SPIE - Mask blanks, absorber materials, defect repair, and curvilinear mask writing.
- Low-n and high-k EUV absorbers - Replacing TaBN absorbers to reduce mask-3D effects at High-NA.
- Multi-beam mask writers - IMS Nanofabrication; curvilinear ILT masks are only writable because multi-beam writers decoupled write time from shot count.
- EUV pellicles - Transmission, thermal load, and why pellicles were the long pole for EUV defectivity.
- Mask 3D effects - Why a reticle at 6× magnification and 6° chief-ray angle is not a thin mask, and what that does to imaging.
- Stochastics in EUV lithography - The photon shot-noise argument: EUV photons are ~14× more energetic than 193 nm photons, so a given dose contains far fewer of them, and randomness becomes a yield-limiting defect mechanism (microbridges, broken lines, missing contacts).
- Metal-oxide resists — Lam / Inpria dry resist - Dry deposition and dry development of metal-oxide resist; higher EUV absorption at lower dose.
- Applied Materials / TEL resist processing - Track systems and the coat/develop side of the resist story.
- Journal of Micro/Nanopatterning, Materials, and Metrology (JM3) - Where resist and stochastics papers live outside conference proceedings.
- ALE and selective deposition for EUV resist improvement (patent) - Illustrative of the "fix the resist with a process module" strategy: selective caps, scum removal, divot fill.
- SADP / SAQP explained - Self-aligned double and quadruple patterning, spacer deposition, mandrel pull, and the pitch walking that results.
- Litho-etch-litho-etch and cut masks - The overlay budget arithmetic that made EUV economically inevitable.
- Directed self-assembly (DSA) - Block copolymers for pitch multiplication and via rectification; a perennial "five years away" technology that keeps finding niche uses.
- Canon nanoimprint lithography - NIL as a low-cost, low-throughput alternative for specific layers and for memory.
- Semiconductor Engineering — Nanoimprint's second act - Realistic assessment of where NIL actually competes.
The mask is no longer a picture of the design. Between the two sits OPC, sub-resolution assist features, source-mask optimization, and increasingly full inverse lithography — a nonconvex optimization run over petabytes of layout, now routinely GPU-accelerated.
- Inverse lithography technology overview - What ILT changes versus rule- and model-based OPC.
- NVIDIA cuLitho - GPU-accelerated computational lithography library, adopted by TSMC and Synopsys; the reason full-chip curvilinear ILT became tractable.
- Siemens Calibre - The dominant production OPC/verification platform.
- Synopsys Proteus / S-Litho - OPC, lithography simulation, and mask synthesis.
- ASML Brion - Tachyon source-mask optimization and LMC, coupled to ASML scanner models.
- ICCAD CAD Contest benchmarks - The annual contest problems (mask optimization, hotspot detection, layout) are the standard public benchmarks in this field.
- Mask optimization literature index — CUHK - Bei Yu's group page; the most complete public bibliography of learning-based OPC/ILT.
Computational lithography is, unexpectedly, one of the healthiest open-source niches in fab-side software — largely because the ICCAD 2013 mask-optimization benchmark gave academia a shared target.
ILT and mask optimization
- OpenILT - PyTorch-based open platform for inverse lithography research, implementing the ICCAD 2013 benchmark lithography model with GPU acceleration. It decomposes the ILT flow into simulation, initialization, optimization, and evaluation, so you can replace one stage without rewriting the rest. The natural starting point.
- OpenFuILT - ISPD 2024 full-chip ILT system with boundary healing, addressing the tile-stitching artifacts that appear when ILT is scaled past a clip. Paired with OpenFuILT-Eval for full-chip scoring.
- TorchLitho - Differentiable computational lithography framework; the imaging model is a differentiable module you can drop into a training loop.
- TorchLitho 2.0 - ASICON 2025 rewrite aimed at full-chip-scale mask optimization with a friendlier API.
- Neural-ILT - CUHK's end-to-end learning-based mask optimizer; the reference implementation of the learned-ILT lineage.
- LithoNet - Learning-based lithography simulator and mask optimizer, useful as a compact baseline.
- DimmiLitho - Pixel-based mask synthesis plus a partially coherent imaging model, in readable Python.
- lithosim - Deliberately minimal lithography simulation and pixel-based OPC tool from the OpenRAM group; good for teaching.
- Neural Lithography - SIGGRAPH Asia 2023 real-to-simulation closed loop, calibrating a learned litho model against measured hardware.
- Neural-ILT / DAMO / GAN-OPC family - The broader learning-based ILT lineage, with code links from the authors' page.
- ILILT — implicit learning of ILT (arXiv) - Recent approach that avoids explicit iterative optimization at inference time.
- Open-source differentiable lithography imaging framework (arXiv) - End-to-end differentiable Abbe/Hopkins imaging, so lithography models can sit inside a training loop.
Benchmarks
- LithoBench - 120k+ layout tiles cropped from real designs or synthesized to spec, with reference implementations of mask-optimization baselines. The closest thing the field has to ImageNet.
Imaging and resist simulators
- K-Litho - TCC/SOCS-based aerial and resist image calculation, including source-mask optimization primitives.
- LithographySimulator - Actively maintained Python tool modeling optical photolithography from first principles.
- Lithography-Simulation - Notebook-style introduction to Hopkins imaging; the gentlest on-ramp to the mathematics. Computational-lithography extends it to 2D.
- Optolithium - Full optical lithography simulator with a GUI covering illumination, mask, projection, and resist development. Archived, still instructive.
- microlith - Partially coherent image simulation shared between microscopy and lithography optics.
E-beam and maskless
- pecebl - E-beam lithography simulation with proximity effect correction; CUDAEBL is the GPU-accelerated variant.
- Raith_GDSII - MATLAB toolkit for driving Raith EBL and FIB systems, maintained by NRC Canada.
- LTK - Lithography toolkit for KLayout, aimed at direct-write jobs.
- ASML_JobCreator - Programmatically generate job files for an ASML PAS 5500 stepper; from the UCSB nanofabrication facility.
- Hacker Fab stepper - Control software for a DLP-based maskless photolithography stepper you can actually build. See DIY and Garage Fab.
Layout I/O for mask work
- KLayout - Not a lithography simulator, but the open-source layout viewer/editor with a Python/Ruby API that most open lithography work uses for GDS/OASIS I/O and DRC-style geometry processing.
- gdstk - Fast C++/Python GDSII and OASIS library; useful for generating test patterns and mask decks programmatically.
- gdsCAD - Python package specifically oriented toward building photolithography mask sets.
- Atomic layer deposition — BALD Engineering - Long-running ALD blog covering precursors, conferences, and industrial adoption; unusually deep archive.
- Area-selective deposition (ASD) - Review covering ASD, atomic layer annealing, and ALE together. ASD is how the industry hopes to get self-aligned structures without extra masks.
- ASD Workshop - The dedicated annual workshop; abstracts are the best index of what selectivity is achievable on which material pairs.
- ALD conference (AVS) - Primary venue for ALD/ALE process chemistry.
- Area-selective ALD of Ru — defect formation mechanisms (PMC) - Concrete example of why selectivity degrades and how it is measured.
- Applied Materials — deposition products - PVD, CVD, ALD, and epi product families; useful for mapping process steps to actual toolsets.
- Lam Research — cryogenic etching - Cryo 3.0 combines cryogenic wafer temperature with pulsed plasma ALE for high-aspect-ratio features; the enabling technology for 3D NAND beyond ~300 layers.
- Atomic layer etching for extreme manufacturing (Springer) - Review of ALE mechanisms and where atomic-scale precision is actually required.
- Cryo-ALE and HAR etch physics - Why sub −100 °C substrate temperature suppresses lateral etch and stabilizes sidewall passivation.
- TEL etch systems - Tokyo Electron's plasma etch portfolio, including their cryogenic HAR approach.
- AVS Plasma Science and Technology - The academic community behind plasma etch modeling; also home to the Journal of Vacuum Science & Technology.
- High-aspect-ratio etch challenges - Bowing, twisting, tilting, and aspect-ratio-dependent etch, explained without a paywall.
- CMP fundamentals - Slurry chemistry, pad conditioning, dishing/erosion, and why CMP dominates defectivity budgets.
- Wafer cleaning and surface preparation - RCA cleans, dilute chemistries, cryo-aerosol, and the pattern-collapse problem at high aspect ratios.
- Ion implantation - Beamline vs. plasma doping, and the shift toward conformal doping for 3D structures.
- Millisecond and laser annealing - Thermal budget is the binding constraint for sequential 3D integration; anneal technology is how you buy activation without diffusion.
- Selective epitaxial growth for source/drain - Strain engineering via SiGe/SiP source-drain, still the main mobility booster.
- Advanced Semiconductor Manufacturing Conference (ASMC) - The manufacturing-focused IEEE/SEMI conference; process module papers with actual fab data.
- SEMI — Materials market data - Wafer, gas, chemical, photoresist, and substrate market sizing.
- Electronic Materials — Merck/EMD, JSR, Shin-Etsu, TOK, Sumitomo - The materials supply chain is more concentrated than the equipment supply chain; resist and mask blank supply are effectively duopolies.
- Ultra-high-purity gases and precursors - Bulk and specialty gas supply, including the fluorinated-gas emissions problem.
- Critical minerals and semiconductor materials - CSIS's economics program tracks gallium, germanium, neon, and rare-earth supply risk.
- Materials Project - Open computed-materials database; the practical starting point for screening dielectric, barrier, and channel candidates.
| Segment | Principal suppliers |
|---|---|
| Lithography scanners | ASML, Canon, Nikon |
| Deposition (CVD/PVD/ALD/epi) | Applied Materials, Lam Research, TEL, ASM International, Kokusai Electric |
| Etch | Lam Research, TEL, Applied Materials, Hitachi High-Tech |
| CMP | Applied Materials, Ebara, TEL |
| Cleans / track | SCREEN, TEL, Lam |
| Process control / metrology | KLA, Onto Innovation, Nova, Hitachi High-Tech, Bruker, Park Systems |
| Ion implant | Applied Materials, Axcelis, SMIT/Sumitomo |
| Bonding / packaging | BESI, ASMPT, EV Group, SUSS MicroTec, Kulicke & Soffa |
| Test / ATE | Advantest, Teradyne, Cohu |
- SEMI — Equipment market data (Worldwide Fab Forecast) - Fab-by-fab capacity, equipment spending, and construction tracking. The industry's standard planning dataset.
- VLSI Research / TechInsights equipment rankings - Annual market-share tables by segment.
At sub-2 nm, a measurement that perturbs the structure or cannot see past the top few nanometers is not a measurement. This section is why metrology capex has grown faster than litho capex.
- CD-SAXS at NIST - Critical- dimension small-angle X-ray scattering is currently the only non-destructive technique that resolves sub-nanometer sidewall angle, pitch walking, inner-spacer geometry, and channel-hole tilt through multi-micron-deep structures.
- Metrology challenges in sub-5 nm nodes - Why optical scatterometry hits opacity and multi-reflection limits and CD-SEM cannot penetrate deep structures without damage.
- X-ray metrology market and technology - XRF, XRD, XPS, and CD-SAXS mapped to the process steps that need them.
- Metrology for next-generation 3D NAND - High-aspect-ratio measurement, which is now a packaging problem too (TSVs, deep vias).
- SPIE Metrology, Inspection, and Process Control - The primary conference; proceedings volumes are the reference literature.
- Atom probe tomography and TEM for devices - Destructive but atomically resolved; how dopant profiles in nanosheets are actually confirmed.
- Hybrid metrology - Combining optical, AFM, and X-ray data into one regression; the practical answer to any single technique being insufficient.
- KLA — inspection and review - Brightfield, darkfield, and e-beam inspection; the reference implementations for the whole category.
- E-beam inspection throughput problem - Why multi-beam e-beam inspection is the most-attempted, least-delivered idea in metrology.
- Voltage contrast and physical failure analysis - How buried opens and shorts are localized before anyone cross-sections a wafer.
- Automated defect classification (ADC) - The first production ML application in fabs, predating the current wave by two decades.
- Yield models — Poisson, Murphy, negative binomial - D0 and clustering factor; the arithmetic behind every chiplet-vs-monolithic argument.
- Statistical process control in semiconductor manufacturing - ASMC is where the practical SPC/APC work is published.
- Run-to-run control and virtual metrology - Predicting a measurement instead of taking it; the highest-value ML deployment in most fabs.
- Yield learning and defect Pareto methodology - How a fab actually decides what to fix next.
- SEMI E10 / OEE definitions - The standard equipment-state model underneath every fab productivity metric.
Memory drives more wafer starts than logic and more advanced-packaging demand than anything except AI accelerators. It also pioneers processes — hybrid bonding shipped in NAND before it shipped in logic.
- SK hynix DRAM roadmap — 4F2 VG and 3D DRAM - The long-range plan: 6F2 → 4F2 with vertical-channel/vertical-gate transistors, then 3D DRAM.
- Samsung — 3D DRAM on the roadmap - Timing and architecture direction.
- Baby steps toward 3D DRAM - Honest assessment of what stacking DRAM actually requires (capacitor-less cells, IGZO channels, or wafer-bonded arrays).
- Lam — learning from NAND for the 3D DRAM transition - Equipment-vendor perspective on which NAND lessons transfer.
- 4F2 DRAM with vertical thin-film transistor (patent) - Patent literature is the best public source on cell architecture specifics.
- NAND flash targets 1000 layers - String stacking, CMOS-under-array vs. CMOS-bonded-array, and the etch/metrology limits.
- Kioxia/SanDisk CBA and YMTC Xtacking - Wafer-bonded periphery is the architecture that made hybrid bonding a volume technology.
- TEL cryogenic etch for 400-layer NAND - Ultra-fast deep etch with substantially lower global-warming-potential emissions.
- JEDEC JESD270-4 — HBM4 - The standard itself: 2048-bit interface per stack, with data rates specified up to 8 GT/s and beyond in the amended revision.
- JEDEC — HBM4 press release - Official summary of bandwidth, efficiency, and capacity targets.
- JEDEC — SPHBM4 - HBM4-level throughput at reduced pin count, aimed at cost-sensitive and mobile-adjacent uses.
- Siemens — HBM3E and HBM4 IC design guide - Design-side treatment: base-die logic process, channel count, and signal integrity.
- EE Times — the push toward custom memory - Custom HBM base dies with embedded logic, and what standardization gives up.
- EE Times — Rambus HBM4E controller and C-HBM4E - The controller side of custom HBM, including UCIe-interfaced variants.
- MRAM, RRAM, PCM and FeFET status - Where each has actually shipped: embedded MRAM in foundry MCU nodes, PCM in storage-class memory, FeFET still mostly in research.
- Hafnium-oxide ferroelectrics - The CMOS-compatible ferroelectric that made FeFET and FeRAM interesting again.
- Compute-in-memory surveys - The main application driver for emerging NVM; search arXiv cs.AR and cs.ET for current surveys.
- Stanford N3XT / monolithic 3D memory-logic - RRAM plus CNFET logic in a monolithic stack.
The longest section, deliberately. Packaging moved from cost-down back-end work to the primary lever on system performance, and it is currently the binding capacity constraint on AI hardware.
- A comprehensive primer on advanced semiconductor packaging - The best single free explainer: wire bond → flip chip → fan-out → 2.5D → 3D, with the reasoning for each transition.
- Heterogeneous Integration Roadmap chapters - Free, authoritative, and organized exactly the way this section is.
- 3D InCites - The trade publication dedicated to advanced packaging. Phil Garrou's IFTLE column is the closest thing the field has to a running technical journal.
- Semiconductor Engineering — Advanced Packaging knowledge center - Terminology plus a decade of linked coverage.
- TechInsights — Advanced packaging and chiplets - Teardown-grounded overview of what is actually inside shipping packages.
- Semiconductor Packaging workshop (open course material) - Workshop repository bridging chip design and packaging, from wire bonding through 2.5D/3D chiplet assembly.
- Semiconductor Packaging fundamentals notes - Course-style notes covering packaging fundamentals.
- Chiplet Marketplace wiki — advanced packaging - Vendor-neutral wiki with a usable taxonomy of package types.
Taxonomy cheat sheet
| Family | Vertical? | Interconnect | Typical pitch | Examples |
|---|---|---|---|---|
| Flip-chip BGA | No | C4 solder bumps | 100–150 µm | Conventional SoC packages |
| Fan-out WLP | No | RDL in mold compound | 5–40 µm | TSMC InFO, ASE FOCoS |
| 2.5D interposer | Side-by-side | Si interposer + µbump | 40–55 µm | TSMC CoWoS-S, Amkor S-SWIFT |
| 2.5D bridge | Side-by-side | Embedded Si bridge | 45–55 µm | Intel EMIB, TSMC CoWoS-L |
| 3D µbump stack | Yes | TSV + µbump | 25–40 µm | HBM stacks, Foveros |
| 3D hybrid bond | Yes | Direct Cu–Cu + oxide | 1–10 µm | TSMC SoIC, Intel Foveros Direct, AMD 3D V-Cache |
| Panel-level | No | RDL on large panel | 5–20 µm | FOPLP, TSMC CoPoS |
- TSMC 3DFabric / CoWoS - Official landing page for CoWoS-S (silicon interposer), CoWoS-R (RDL interposer), CoWoS-L (interposer with embedded local silicon interconnect bridges), InFO, and SoIC.
- Intel EMIB - Embedded Multi-die Interconnect Bridge: a small silicon bridge embedded in organic substrate, avoiding a full-reticle interposer and its TSVs.
- Intel EMIB with glass core (NEPCON 2026) - Bridge plus glass core in one package; a preview of where 2.5D substrates are heading.
- Amkor S-SWIFT and S-Connect - OSAT alternatives to foundry-owned 2.5D flows.
- Samsung I-Cube / H-Cube - Samsung's 2.5D families.
- SemiAnalysis — packaging developments from ECTC - Conference readout on where interposer and bridge technology actually is.
- Interposer design considerations - Micro-bump pitch, RDL line/space, and reticle-stitching limits for large interposers.
Hybrid bonding replaces solder microbumps with direct copper-to-copper bonds surrounded by dielectric-to-dielectric bonds. That removes the underfill, removes the bump height, and lets interconnect pitch scale below 10 µm — into a regime where vertical wires start to look like on-die wires.
- Intel — Foveros Direct 3D technical brief (PDF) - Vendor technical brief on bumpless Cu–Cu bonding, sub-10 µm pitch, and the design rules that follow.
- TSMC SoIC - System on Integrated Chips: bumpless front-end 3D stacking, currently around 9 µm pitch in production and used together with CoWoS-L in flagship AI parts.
- Semiconductor Engineering — Making hybrid bonding better - The practical problems: dishing control, surface activation, particle sensitivity, and D2W placement accuracy.
- TechInsights — Hybrid bonding, tomorrow's interconnect - Cross-sections of shipping hybrid-bonded devices.
- Adeia (Xperi) DBI / DBI Ultra - The licensed direct bond interconnect technology underneath much of the industry's W2W and D2W capability.
- Yole — hybrid bonding interview with Adeia - Market and roadmap framing.
- IBM — D2W and W2W hybrid bonding below 25 µm pitch - Research-lab account of building the bonding system, not just using one.
- AMD 3D V-Cache - The first high-volume consumer product built on hybrid-bonded logic-on-logic stacking; a useful concrete reference design.
- ECTC — Electronic Components and Technology Conference - The packaging field's IEDM. Every bonding, pitch, and reliability record is announced here first.
Pitch scaling, roughly. Microbump flip-chip bottoms out near 25–40 µm because solder needs volume and standoff. Hybrid bonding starts around 10 µm and has demonstrated 2 µm and below in research. Intel has publicly described Foveros pitch progressing from ~50 µm (2020) to ~9 µm, with ~3 µm as a stated goal. Each halving of pitch is a 4× increase in vertical bandwidth density.
- TSMC InFO - Integrated Fan-Out; the technology that put TSMC in packaging and shipped in mobile APs before anything else.
- Fan-out wafer-level packaging overview - Chip-first vs. chip-last, die shift, and warpage — the three problems FOWLP always has.
- TSMC CoPoS — chip-on-panel-on-substrate - Panel-level packaging as the escape from round-wafer area inefficiency for very large packages.
- Panel size standardization - 310 × 310 mm, 510 × 515 mm, and 600 × 600 mm are converging as the industry panel formats.
- FOPLP economics - Yole's packaging reports are the standard source for panel-vs-wafer cost crossover analysis.
- Glass core substrates — the new race - Why glass: better dimensional stability and flatness than ABF organic cores, enabling finer RDL and larger bodies.
- Absolics (SKC) glass substrate production - The first dedicated glass-substrate mass-production line, in Georgia.
- MIT Technology Review — future AI chips on glass - Accessible framing of the transition and its remaining obstacles (brittleness, via formation, handling).
- IDTechEx — glass interposers and substrates - Comparison against silicon interposer and organic RDL on cost, loss, and thermal expansion.
- ABF substrate supply - Ajinomoto build-up film and the substrate-supply bottleneck that has repeatedly gated GPU shipments.
- RDL scaling — line/space roadmap - HIR's interconnect chapter has the authoritative RDL dimension roadmap.
- Through-silicon via fundamentals - Via-middle vs. via-last, Cu pumping, keep-out zones, and the stress effects TSVs impose on nearby devices.
- Wafer thinning and temporary bonding - Backside power and 3D stacking both require thinning to single-digit micrometers on a carrier.
- Thermocompression bonding and fluxless TCB - Where TCB still wins over hybrid bonding, and the fluxless transition.
- BESI hybrid bonding platforms - Die-to-wafer hybrid bonders and their placement-accuracy specifications.
- EV Group bonding technology - Wafer-to-wafer fusion and hybrid bonding, plus the metrology to verify alignment.
- ASMPT advanced packaging - High-throughput die attach and TCB.
- 2 µm pitch D2W hybrid bonding (ECTC 2025) - Surface protection during thinning and singulation is the enabling trick; see the ECTC 2025 program.
Stacking dies multiplies power density and buries the hot layer under silicon. Thermal is now a first-order architectural constraint, not a mechanical afterthought.
- 3D-ICE - EPFL's transient thermal simulator for stacked 3D ICs, including inter-tier microchannel liquid cooling. Widely used in research.
- PACT — Parallel Compact Thermal Simulator - SPICE-based parallel thermal simulation from standard-cell to architecture level, extensible to 3D stacking and liquid cooling by editing the thermal netlist.
- HotSpot - The long-standing architecture-level compact thermal model; still the baseline everything else is compared against.
- MFIT — multi-fidelity thermal modeling for 2.5D/3D chiplets (arXiv) - Trading accuracy for speed in chiplet thermal exploration.
- Cool-3D — thermal-aware early design space exploration - End-to-end framework for microfluidic-cooled 3D ICs.
- Open-source thermal modeling tools (DAC BoF slides, PDF) - A guided tour of the open thermal tool landscape by one of its main authors.
- Vertical power delivery for HPC packages (arXiv) - Design framework for delivering hundreds of amps vertically through a package.
- Warpage and thermomechanical stress - CTE mismatch across die, underfill, mold compound, and substrate; the reason large packages fail assembly before they fail electrically.
- Direct-to-chip liquid cooling and immersion - OCP's cooling workstream; where package-level thermal meets datacenter facilities.
- TSMC COUPE - Compact Universal Photonic Engine: an electronic IC stacked on a photonic IC using SoIC bumpless bonding, then integrated with CoWoS. Roadmapped from ~0.5 Tb/s/mm toward ~4 Tb/s/mm.
- Tom's Hardware — CPO foundry roadmaps compared - TSMC, Intel, Samsung, and GlobalFoundries approaches side by side.
- EDN — where CPO stands in 2026 - Realistic status check on deployment.
- SemiAnalysis — Co-Packaged Optics: scaling with light - Long-form economic and technical analysis of the CPO transition.
- IFTLE — TSMC integrated CoWoS and COUPE - Packaging-community perspective with cross-sections.
- OIF — co-packaged optics frameworks - Where the electrical-optical interface agreements are written.
- gdsfactory - Open-source Python framework for photonic and analog layout; the practical entry point for building a PIC layout you can actually tape out.
- gplugins — DEVSIM, Meep, and TCAD plugins for gdsfactory - Ties photonic layout to device and EM simulation.
- TSMC advanced packaging capacity tracking - CoWoS and SoIC capacity expansion reporting; capacity numbers here move markets and change quarterly, so treat any single figure as a snapshot.
- ASE Group - Largest OSAT; FOCoS, VIPack, and fan-out capacity.
- Amkor Technology - Second-largest OSAT, with US advanced packaging investment.
- JCET, Powertech (PTI), SPIL, Tongfu Microelectronics — The rest of the top-tier OSAT landscape.
- SEMI Packaging market data - Capacity and materials consumption by package family.
- IMAPS - The microelectronics packaging professional society; its Device Packaging Conference is the applied counterpart to ECTC.
Chiplets are an economic response to three facts: yield falls superlinearly with die area, SRAM and analog stopped scaling with logic, and High-NA halves the reticle field. Splitting a design only pays if the die-to-die interface is cheap enough in power, area, and latency — which is what all these standards are about.
- UCIe — Universal Chiplet Interconnect Express - The de facto standard: standard package and advanced package variants, PHY/adapter/protocol layer stack, streaming and PCIe/CXL protocol mappings, and a compliance program.
- UCIe on Wikipedia - Concise, accurate summary of the layer stack and bump-pitch tiers if you do not want to read the specification.
- Bunch of Wires (BoW) — OCP ODSA - The open, royalty-free alternative optimized for organic substrates; simpler PHY, no advanced package required.
- Intel AIB / AIB 2.0 - Advanced Interface Bus; the open-sourced DARPA CHIPS-era die-to-die PHY. Historically important and still a usable reference.
- OpenHBI - HBM-derived open die-to-die interface for short-reach, high-density links.
- OIF CEI-112G / CEI-224G - The long-reach SerDes agreements that chiplet XSR and USR links are derived from.
- IEEE P3405 chiplet standards - Emerging IEEE work on chiplet interface and interoperability specifications.
- OIF/MSA short-reach optical chiplet interface - WDM-based optical chiplet interconnect for scale-up CPO, backed by the major hyperscalers and accelerator vendors.
- ucb-bar/ucie - Open-source digital implementation of the UCIe 1.1 specification from UC Berkeley.
- ucb-ucie/ucieanalog - The analog/mixed-signal companion to the digital UCIe implementation.
- google/open-chiplet - Components for building an interoperable chiplet using open and industry-standard interfaces.
- tenstorrent/aou-rtl - AXI-over-UCIe bridge RTL, targeting the UCIe 3.0 Flit-Die Interface. A rare open, production-oriented D2D bridge.
- Zero ASIC — lowering the barrier to chiplets - Write-up of an open UCIe-lite D2D generator, simulated with Verilator, Icarus, Xyce, and Switchboard.
- Switchboard - High-performance open co-simulation library for stitching RTL, C++, and Python models across chiplet boundaries.
- Intel AIB PHY hardware - Open RTL and documentation for the AIB generation of die-to-die interfaces. The CHIPS Alliance fork at chipsalliance/aib-phy-hardware is the one under active stewardship.
- OpenHBM - Open-source HBM4 memory subsystem targeting JEDEC JESD270-4A: controller, PHY shim, DFT, RAS, and security. A rare open implementation of a bandwidth-class memory interface rather than a toy.
- UMI — Universal Memory Interface - Transaction-level interface standard for composing chiplets and accelerators, designed to sit above a D2D PHY.
- EBRICK demo - Worked example of packaging a design as a reusable chiplet "brick" with a standard interface and footprint.
- logikbench - Digital logic benchmark suite for comparing synthesis and place-and-route across tools and technologies.
- Chipyard - Berkeley's SoC framework; the usual host environment for integrating open D2D IP into a real design.
- Chiplet Actuary - Quantitative cost model for multi-chiplet systems, the first to model die-to-die overhead and NRE cost explicitly. Paper: arXiv:2203.12268.
- Gemini — mapping and architecture co-exploration - HPCA 2024 framework co-exploring architecture and mapping for large DNN chiplet accelerators under monetary-cost, performance, and energy objectives. Uses Chiplet Actuary for package cost.
- Gemini paper (PDF) - Full method description.
- CATCH - Cost Analysis Tool for Co-optimization of Chiplet-based Heterogeneous systems (UCLA NanoCAD). Models wafer cost, yield, known-good-die test, assembly, and packaging together, so you can see where disaggregation stops paying. Paper: arXiv:2503.15753.
- ChipletPart - Cost-aware partitioner for 2.5D systems: multi-way partitioning, heterogeneous technology assignment, and IO-reach-aware floorplanning in one loop. Paper: arXiv:2507.19819.
- OCP chiplet cost model - Industry-consensus cost model covering materials, test, known-good-die, and operations, published for supply-chain and engineering trade-offs.
- Yield and cost arithmetic for disaggregation - When splitting a die actually saves money once packaging, test, and KGD costs are included.
- Die-per-wafer and yield calculators - The arithmetic behind every chiplet business case: gross die, edge loss, and defect-density yield models (Poisson, Murphy, negative binomial).
- Design approach for energy-efficient D2D interfaces (ISLPED) - pJ/bit budgets across interface choices.
- Open3DFlow - Open-source 3D IC design platform built on existing open EDA tools, with TSV modeling, thermal analysis, and signal-integrity assessment for chiplet designs. A second implementation adds abstractions for simulating hybrid-bonded 3D structures on an OpenROAD 2D backend.
- TAP-2.5D - Thermally-aware chiplet placement for homogeneous and heterogeneous 2.5D systems, using simulated annealing to trade inter-chiplet wirelength against peak temperature. One of the few tools that treats thermal as a placement objective rather than a post-hoc check.
- BookSim2 - Cycle-accurate interconnection network simulator; the standard tool for modeling chiplet NoC/NoP topologies.
- gem5 - Full-system architecture simulator, commonly extended for chiplet and disaggregated-memory studies.
- Timeloop / Accelergy - Mapping and energy estimation for accelerator architectures; pairs naturally with chiplet partitioning studies.
- SIAM and chiplet accelerator simulators - Chiplet-based in-memory-computing accelerator simulation; search arXiv cs.AR for the current generation.
- AuthenTree — distributed trust for chiplet SiPs (arXiv) - Architecture work on authenticating chiplets from multiple vendors.
No open-source flow currently signs off a 3D stack. These are the tools that do.
- Synopsys 3DIC Compiler - Unified multi-die planning, implementation, and analysis in one database.
- Cadence Integrity 3D-IC - 3D-IC planning platform with integrated thermal and early feasibility analysis.
- Siemens Innovator3D IC - Multi-die planning, substrate/interposer co-design, and package-aware signoff.
- Siemens Calibre 3DSTACK - Physical verification across die boundaries, including bonded-interface checks.
- Ansys RedHawk-SC and Icepak - Multiphysics: power integrity, electromigration, thermal, and warpage for stacked assemblies.
- Keysight ADS / EMPro - Package and interposer electromagnetic modeling.
- Siemens Tessent Multi-die - IEEE 1838-based DFT across a stack, including pre-bond, mid-bond, and post-bond test.
- Semiwiki — DFT moves up to 2.5D and 3D IC - What changes in the DFT flow when the design spans dies.
- OpenROAD - The open RTL-to-GDSII physical design engine: floorplanning, placement, CTS, routing, and timing. The centerpiece of the open flow.
- OpenROAD-flow-scripts - Reference flow with working designs on multiple open PDKs; the fastest way to get an end-to-end run.
- LibreLane - The community-maintained successor to OpenLane 2, an RTL-to-GDSII flow built around OpenROAD with Nix-based reproducibility.
- OpenLane - The original OpenLane flow; still the reference for many published tapeouts.
- Yosys - Open synthesis framework; the front end of nearly every open flow.
- SiliconCompiler - Build-system-style hardware compilation framework that abstracts over multiple tools, flows, and PDKs.
- Magic VLSI - Layout editor with built-in extraction and DRC; the workhorse of open analog and custom layout.
- Netgen - LVS for open flows.
- KLayout - Layout viewer, editor, and scriptable DRC engine; the format Swiss army knife of the field.
- OpenRAM - Open memory compiler; SRAM generation for open PDKs.
- Verilator - The fastest open Verilog/SystemVerilog simulator, and the standard for chiplet co-simulation harnesses.
- cocotb - Python coroutine-based verification, widely used for D2D protocol testing.
- ngspice - Open SPICE simulator with BSIM-CMG support.
- Xyce - Sandia's parallel SPICE-class simulator, built for very large circuits including package/PDN networks.
- Coriolis - LIP6's complete open physical design toolchain, an independent alternative to OpenROAD.
- Awesome open source hardware tools - A broader index if you need the front-end tooling this list skips.
Timing and signoff
- OpenSTA - The static timing analysis engine used inside OpenROAD; also usable standalone. The OpenROAD fork tracks flow-specific changes.
- OpenTimer - High-performance parallel timing analyzer, and the reference implementation for several TAU contest problems.
- Parser-SPEF - Fast header-only SPEF parser, for when you need to consume extracted parasitics yourself.
- Tatum - Flexible STA engine from the VTR project.
Analog and mixed-signal
- Xschem - Schematic capture for custom analog design with SPICE, Verilog, and VHDL netlisting. The front end of the open analog flow.
- OpenFASOC - Automated analog generation: describe a temperature sensor or LDO by specification and get a placed-and-routed layout.
- ALIGN - Analog layout automation from netlist to GDS, from the DARPA IDEA program.
- MAGICAL - Machine-generated analog IC layout; the academic counterpart to ALIGN.
- VA-Models - Collection of Verilog-A device models that work with OpenVAF and ngspice; the practical starting point for custom compact models.
- qflow - Complete end-to-end digital synthesis flow; the lightweight predecessor to OpenLane, still useful for small designs.
- SkyWater SKY130 PDK - The first fully open, manufacturable PDK; 130 nm, with a large body of taped-out designs.
- GlobalFoundries GF180MCU PDK - Open 180 nm PDK.
- IHP Open PDK (SG13G2) - Open 130 nm BiCMOS PDK with SiGe HBTs — notable because it includes usable RF devices, which SKY130 does not.
- open_pdks - The installer that assembles open PDKs into forms the open tools actually consume.
- Tiny Tapeout - Multi-project shuttle that puts small open designs on real silicon for a few hundred dollars. Recent shuttles have used IHP SG13G2 and SkyWater 130, with GF180 under evaluation.
- Tiny Tapeout news and shuttle status - Where to check which shuttles are open and which PDKs are supported right now.
- ChipFoundry - Shuttle operator that took over open-silicon shuttle service after Efabless wound down. Worth reading the current terms before planning a tapeout.
- ASAP7 - 7 nm predictive PDK; the standard academic vehicle for sub-10 nm physical design experiments (not manufacturable). The r1p7 release is the version most published results are built on, and ASAP7_for_KLayout adds the technology files needed to view and edit it.
- FreePDK45 / FreePDK15 - Older predictive kits, still widely used in teaching and in reproducing published results. FreePDK45_for_KLayout and SKY130_for_KLayout provide matching KLayout technology setups.
- OpenRPDK28 - Open process design kit for a 28 nm process; one of the few open kits below 45 nm.
- ICS55 open PDK - 55 nm CMOS open-source PDK (Apache 2.0) from ICsprout, backed by the company's own 300 mm pilot line. The most advanced node released as an open, foundry-backed kit so far — but read the terms: it is a preview, open-EDA compatibility is still being worked on, and commercial mass production use is currently excluded.
- lambdapdk - A library of open PDK packages wrapped in a uniform interface, so a design can move between processes without rewriting the flow.
- volare - Version manager and builder for the SKY130 and GF180MCU PDKs. Pin your PDK version the way you would pin a compiler.
- IIC-OSIC-TOOLS - All-in-one Docker image with the open analog and digital flows preinstalled and SKY130, GF180, IHP SG13G2 and SG13C5 PDKs bundled. The single fastest way to get a working environment, and the one most tutorials assume.
- ihp-sg13g2 AMS chip template - End-to-end analog/mixed-signal tutorial and project skeleton for the IHP open PDK, from schematic to submitted GDS.
- IHP Open PDK documentation and FMD-QNC tapeouts — Reference designs actually fabricated on the IHP open process.
- Caravel - The SoC harness that open MPW submissions are wrapped in, providing the padframe, management core, and test infrastructure around your design. The original Efabless repository is the historical reference; ChipFoundry maintains the active fork.
- SSCS Chipathon - IEEE Solid-State Circuits Society open-source design program: design, tape out, test, publish. Includes full course material.
- Tiny Tapeout support tools and the IHP submission template — The build infrastructure and project skeleton behind the shuttle.
- pavona - Library of modular, tapeout-proven, secure-by-default open silicon blocks; useful when you need IP you can trust in a shuttle submission.
- Open3DFlow - Open 3D IC platform with TSV modeling, thermal, and SI analysis layered onto open EDA tools.
- Cool-3D - Thermal-aware early-phase design space exploration for microfluidic-cooled 3D ICs.
- Compact-2D / Pin3D / Cascade2D - The Georgia Tech lineage of pseudo-3D physical design methods that fold a 2D placement into two tiers; search for the authors' releases, which appear intermittently.
- MFIT — multi-fidelity chiplet thermal modeling - Practical if you need thermal inside an optimization loop rather than as a signoff check.
- OpenROAD 3D and multi-die research branches - Watch the org rather than any single repository; 3D support arrives as separate projects.
- Open Source EDA Birds of a Feather - Annual DAC session; the slide archive is the best single map of what open EDA can and cannot do each year.
The tools below are 2D, but they are the substrate every 3D and chiplet method builds on, and most published 3D results are reported against them.
- DREAMPlace - GPU-accelerated analytical placement that reframed placement as a deep-learning training problem. Orders of magnitude faster than the CPU placers it replaced, and the baseline nearly every placement paper now compares against.
- Xplace - Fast, deterministic GPU placement framework with detailed-routability and timing optimization.
- DG-RePlAce - GPU-accelerated version of RePlAce, the global placer inside OpenROAD.
- TritonPart - Open hypergraph partitioner; the front end to most partition-driven 3D and chiplet flows.
- CU-GR - Global routing tool from CUHK, a common research baseline.
- PROBE3.0 - Methodology for measuring the true quality gap between design tools and achievable results, by generating designs with known optimal solutions. The honest answer to "how good is my placer really?"
- RosettaStone - Translations between the enablements and formats that make cross-tool comparison possible.
- FakeRAM2.0 - Generates plausible memory macro abstracts (LEF/Liberty) when you have no memory compiler, which is the normal situation in academic flows.
- NanGate45 and ASAP7 Synopsys enablements — Reference setups for reproducing published commercial-tool results.
- PlacementEssentialReadings - Curated reading list for physical design placement; a good syllabus if you are entering the field.
- ORFS-Agent - LLM-driven autotuning of OpenROAD flow parameters, an early example of agents doing PPA search.
- ISPD 2026 contest - Post-placement buffering and sizing. The ISPD/ICCAD contest problems are how this field distributes benchmarks.
- iEDA - Independent open EDA infrastructure covering netlist to GDS, from the Chinese open-source EDA community.
- mflowgen - Modular ASIC/FPGA flow generator; builds reproducible tool flows out of composable node graphs.
- Hammer - Berkeley's physical design flow abstraction, letting one RTL design target multiple technologies and tool vendors.
- gdstk - Fast GDSII/OASIS manipulation in C++/Python.
- gdspy - The predecessor; still common in older scripts.
- gdsfactory - Layout-as-code framework with a strong photonics and packaging component library.
- OpenVAF - Open Verilog-A compiler, enabling open compact-model development.
- Hdl21 - Python-embedded hardware description for analog and mixed-signal generators.
- FastCap / FastHenry (via FastFieldSolvers) - Classic capacitance and inductance extraction; still useful for interposer and package parasitics.
- OpenEMS - Open FDTD electromagnetic solver, usable for package and interposer structures.
- Pyaedt - Python API to Ansys Electronics Desktop, if you have the commercial license and want scripted package analysis.
- KLayout-PEX - Parasitic extraction inside KLayout, filling one of the larger gaps in the open signoff flow.
- gdscheck - Fast standalone DRC engine for GDSII layouts, written in Rust.
- gds2Para - Layout parsing and parameter extraction from GDSII, aimed at parasitic and interconnect analysis.
- xsection - Generates process cross-sections from a layout and a process description; the fastest way to sanity-check a stack-up. klayout_pyxs is the Python port.
- GDS3D - Renders GDSII layouts as 3D structures using a process stack description. Genuinely useful for explaining a BEOL stack to anyone.
- gdsjam - Web-based collaborative GDSII viewer, for reviewing layout without everyone installing a toolchain.
- phidl - Python GDS layout and CAD geometry creation with an unusually friendly API; the basis of several hobby and research mask flows.
- gdshelpers - Pattern generation for nanostructuring and integrated optics.
- kfactory - Layout-as-code in the gdsfactory style, on a KLayout backend, for large hierarchical layouts.
- Synopsys Sentaurus - The industry-standard process and device TCAD suite; effectively required for advanced-node device development.
- Silvaco Victory - The main alternative, with process, device, and atomistic modules.
- Cogenda Genius / Visual TCAD - Lower-cost commercial TCAD, common in academia.
- Global TCAD Solutions (GTS) - Specializes in variability, reliability, and nano-device simulation.
- Synopsys QuantumATK - Atomistic simulation for materials, interfaces, and 2D-material devices.
- Applied Materials Ginestra - Multiscale materials-to-device simulation, strong on reliability and emerging memory.
- Lam SEMulator3D - Virtual fabrication: predictive 3D process modeling used to debug integration schemes before running wafers. The most directly "fab" of the commercial simulators.
- TCAD Central — software index - Community-maintained index of TCAD tools, commercial and free.
- DEVSIM - Finite-volume TCAD device simulator, Apache 2.0 licensed, scriptable from Python. The most practical open device simulator.
- Charon - Sandia's open-sourced TCAD device code, built on Trilinos with finite-element and finite-volume discretizations and parallel nonlinear solvers.
- ViennaPS - Process and topography simulation library modeling 2D/3D surface evolution during etching, deposition, and oxidation, combining level-set surface evolution with Monte Carlo ray tracing for flux. Python bindings included.
- ViennaLS - The sparse-field level-set engine underneath ViennaPS, using hierarchical run-length encoding for memory efficiency.
- ViennaRay - The Monte Carlo ray tracer that computes particle flux to the evolving surface; what makes ViennaPS etch models directional.
- ViennaCS - Volumetric cell-set representation layered on the level-set surfaces, for models that need material composition below the surface (implant, diffusion, mixed-material etch).
- ViennaEMC - Ensemble Monte Carlo carrier transport for semiconductors and metals; the transport counterpart to the topography stack.
- ViennaChem - Derives surface-kinetics models from chemical reaction equations, so etch chemistry can be specified declaratively.
- ViennaFit - Fits ViennaPS process models to experimental cross-sections. Calibration is the step that decides whether process simulation is useful or decorative.
- DRIESequences - Emulation models for the DEM, DREM, and DREAM deep reactive-ion etch sequences.
- ViennaHRLE - The hierarchical run-length encoded data structure underpinning the level-set memory efficiency.
- ViennaTools organization - The full process-simulation stack in one place.
- ViennaPS paper (SoftwareX) - Describes the architecture and validation cases.
- pytaurus - Python wrapper around Synopsys Sentaurus, for scripting commercial TCAD sweeps from a normal toolchain. Requires a Sentaurus license.
- NanoTCAD ViDES - Open NEGF-based simulator for nanoscale and 2D-material devices.
- Kwant - Quantum transport in tight-binding systems; useful for nanowire and 2D-channel studies.
- NEMO5 - Purdue's multiscale nanoelectronics modeling tool.
- gplugins DEVSIM notebook - Worked example of driving DEVSIM from a layout-first workflow.
- LAMMPS - Molecular dynamics; used for etch/deposition surface chemistry, thermal transport, and thin-film mechanics.
- Quantum ESPRESSO - Plane-wave DFT; the workhorse for band structures of candidate channel and barrier materials.
- VASP - Commercial DFT, the de facto standard in industrial materials groups.
- GPAW and ASE - Python-native DFT and atomistic simulation environment; the easiest on-ramp for scripted materials screening.
- pymatgen - Materials analysis library behind the Materials Project.
- Materials Project - Open computed database of ~150k+ inorganic materials with band gaps, elastic constants, and phase diagrams.
- NOMAD and AFLOW - Alternative materials data repositories, useful for cross-checking.
- Exploring transport in APAM-enabled pn junctions (arXiv) - Example of atom-precision device modeling connecting DFT to TCAD.
- Meep - Open FDTD solver from MIT; the standard free tool for photonic component simulation.
- MPB - Photonic band structure computation.
- openEMS - Open FDTD for RF, package, and interconnect structures.
- scikit-rf - RF/microwave network analysis in Python; practical for de-embedding package S-parameters.
- Ansys Lumerical - The commercial photonic simulation standard, relevant for co-packaged optics work.
- awesome-ai4eda - Curated bibliography of AI for EDA papers; the best entry point to the literature.
- CircuitNet - Open dataset for ML in EDA: 10k+ samples from commercial tool runs on open RISC-V designs, with labels for routability, IR drop, and timing.
- CircuitNet 2.0 (ICLR 2024) - Extended to CPU, GPU, and AI-chip designs in a 14 nm FinFET flow.
- CircuitNet paper (arXiv) - Original dataset description.
- Circuit Training (Google) - Open reinforcement-learning framework for chip floorplanning, released alongside the Nature placement paper.
- OpenABC-D - Large-scale dataset for learning logic synthesis; pairs AIG designs with synthesis recipes and QoR labels.
- EDALearn — RTL-to-signoff ML benchmark (arXiv) - Benchmark aimed at reproducibility across the whole flow.
- MLCAD symposium - The dedicated ML-for-CAD venue, with annual contests.
- ICCAD CAD Contest - Long-running contest whose problem sets became the field's standard benchmarks.
- EPFL logic synthesis benchmarks - The reference combinational benchmark suite.
- awesome-AIEDA-works - A second AI4EDA bibliography, organized by flow stage rather than by method.
- CircuitOps - Turns EDA design data into labeled property graphs, so ML pipelines can consume netlists, placement, and timing without bespoke parsers. The unglamorous piece that makes the rest reproducible.
- TimingPredict - Graph neural network for pre-routing timing prediction, structured after a real timing engine rather than treating the netlist as a generic graph.
- GNN4REL - Graph neural networks predicting circuit reliability degradation from process variation and aging (TCAD 2022).
- OpenILT - PyTorch platform for ILT research with GPU acceleration and ICCAD13 benchmark models.
- LithoBench - Benchmark suite for AI computational lithography with 100k+ clips.
- Generic lithography modeling with optics-inspired neural networks (arXiv) - Physics-informed architecture that generalizes across process conditions.
- ILILT (arXiv) - Implicit learning of ILT.
- Differentiable lithography imaging framework (arXiv) - Makes the imaging model itself trainable.
- NVIDIA cuLitho - Production GPU acceleration for computational lithography.
- Hotspot detection benchmarks — ICCAD 2012/2016 - The canonical layout-hotspot datasets.
- Virtual metrology - Predicting wafer measurements from equipment sensor traces; the highest-ROI fab ML application.
- Automated defect classification with ML - Modern deep-learning ADC versus the rule-based systems it replaces.
- WM-811K wafer map dataset - 811,457 wafer maps from a real 300 mm line across 46,293 lots, with eight labeled defect patterns. The canonical public dataset in this area.
- WM-811K benchmark implementations - Integrated framework comparing CNN, DenseNet, MobileNet, and ResNet variants on the dataset.
- Wafer defect classification reference repo - Clean baseline implementation.
- Defect_KAN - EfficientNet + spatial pyramid pooling + Kolmogorov-Arnold network on WM-811K, with Grad-CAM interpretability.
- Wafer map defect classification with tiny vision transformers (arXiv) - Recent architecture comparison on the same benchmark.
- Autoencoder augmentation for wafer maps (arXiv) - Addresses the severe class imbalance that dominates this dataset.
- Domain adaptation with minimal manufacturing data (arXiv) - The realistic fab problem: very few labeled examples of the defect you care about.
- DAGM 2007 defect dataset - Classic optical surface inspection benchmark, still used for pretraining.
- WaPIRL - Self-supervised pretraining for wafer bin map defect classification. The right approach when unlabeled maps are abundant and labels are not, which is every real fab.
- WaferDC - Long-tailed detection and classification of wafer defects from SEM images, robust to varying image backgrounds (EAAI 2025).
- MixedWM38 vision transformer baseline - Worked example on the mixed-type defect dataset, where a single wafer carries superimposed patterns — the realistic case that WM-811K's eight clean classes understate.
- WaferMap - Additional wafer map defect dataset and models.
- Semiconductor-Fault-Detection - Classifier built on real foundry process data rather than images; a useful counterpoint to the vision-heavy literature.
wafermaptopic on GitHub - Live index of wafer-map tooling and models.
Wafer map and defect file tooling
- klarfkit - Read, plot, and edit KLARF files, the KLA-defined format that inspection tools emit. If you work with real inspection output rather than Kaggle exports, you need this.
- wafermap - Python package for plotting wafer maps with correct notch, edge exclusion, and die grid handling.
- wfmap - Wafer map visualization built on Pandas and Bokeh.
- uia-wafermap - Shot map and wafer map rendering in JavaScript, for building web dashboards.
- stdf2map - Converts STDF test data into wafer bin maps, closing the loop between test and inspection views of the same wafer.
- VerilogEval (NVIDIA) - The standard benchmark for LLM Verilog generation, from ICCAD 2023.
- Revisiting VerilogEval (arXiv) - Updated harness and results as models improved past the original benchmark.
- RTLLM - Open benchmark for RTL generation from natural language, with syntax, functionality, and quality metrics.
- ChipBench (arXiv) - Next-generation benchmark with realistic hierarchical modules, debugging cases, and reference-model tasks across Python, SystemC, and CXXRTL — built because earlier benchmarks saturated.
- ChipVerilog (arXiv) - Large OpenCores-derived benchmark for Verilog RTL generation.
- LLM4ChipDesign - Curated collection of LLM-aided hardware design and verification work.
- LLM4IC - NYU's work on LLMs in chip design with a security and trust focus.
- Agentic hardware verification token allocation (arXiv) - Empirical study of where inference compute actually helps in verification agents.
- SemiKong - Open domain-specific model trained on semiconductor process and equipment knowledge rather than RTL. Aimed at etch and deposition process engineering questions, which is a different problem from code generation.
- LLM4Chip - End-to-end chip design and generation with LLMs using reward-driven reinforcement learning.
- ORFS-Agent - Agent that tunes OpenROAD flow parameters, one of the more concrete demonstrations of agents doing real PPA optimization.
- Generative AI for semiconductor design - Reference engineering-assistant architecture over semiconductor documentation.
| Dataset | Domain | Notes |
|---|---|---|
| WM-811K | Wafer map defects | 811k maps, 8 defect classes, real 300 mm line |
| MixedWM38 | Wafer map defects | 38 classes including mixed-type patterns |
| CircuitNet / 2.0 | ML for EDA | Routability, IR drop, timing labels; 14 nm flow |
| OpenABC-D | Logic synthesis | Synthesis recipes + QoR |
| LithoBench | Computational litho | 100k+ mask-optimization clips |
| ICCAD13 benchmark | ILT/OPC | The reference litho model for ILT research |
| SMT2020 | Fab scheduling | Full 300 mm fab models, HV/LM and LV/HM scenarios |
| EPFL benchmarks | Logic synthesis | Arithmetic and control combinational circuits |
| VerilogEval | LLM RTL generation | Spec-to-RTL, standard reporting |
| Trust-Hub | Hardware security | Trojan benchmarks, side-channel datasets |
| Materials Project | Materials | Computed properties for screening |
A leading-edge fab is a re-entrant flow shop with 1,000+ process steps, hundreds of tools, lot-level priorities, and equipment that requires qualification after every maintenance event. The scheduling problem is genuinely one of the hardest in industrial engineering.
- Factory Physics (Hopp & Spearman) - Little's Law, the VUT equation, and the cycle-time/utilization tradeoff that governs every fab planning decision.
- Cycle time and WIP management in wafer fabs - ASMC proceedings are the applied literature here.
- Winter Simulation Conference — semiconductor track - The main venue for fab simulation and scheduling research; papers are open in the INFORMS/IEEE archives.
- Re-entrant flow shop scheduling literature - The theoretical framing of the problem.
- OEE and equipment productivity (SEMI E10/E79) - Standard state model and productivity definitions.
- SMT2020 — a semiconductor manufacturing testbed - The modern successor to the MIMAC datasets: full 300 mm fab models with 500+ operations and 1,000+ machines, in high-volume/low-mix and low-volume/high-mix variants.
- PySCFabSim - Customizable open-source Python simulator for semiconductor fab scheduling research, compatible with SMT2020.
- PySCFabSim overview (PDF) - Design rationale and performance.
- MiniFab model - The small Intel/ASU testbed: 6 steps, 5 machines, batching. The standard sanity-check problem before scaling to SMT2020.
- Scalability of RL for fab dispatching (arXiv) - Compares open-source fab models against real industry datasets; a useful reality check on published RL results.
- Semiconductor fab scheduling with self-supervised and RL (arXiv) - Representative modern approach.
- SimPy - Discrete-event simulation in Python; the usual substrate for custom fab models.
- JobShopLib - Job-shop scheduling library with RL environments; a reasonable starting point before committing to a full fab model.
- OR-Tools CP-SAT - The practical constraint solver for scheduling subproblems (batching, qual-state-aware assignment, maintenance windows).
- secsgem - Pure-Python SECS/GEM implementation covering SEMI E5 (SECS-II), E30 (GEM), and E37 (HSMS), with no external dependencies. The only widely-used open implementation of fab equipment communication.
- secsgem documentation - Includes a working host/equipment example, which is the fastest way to understand the protocol stack.
- go-secs - SECS-II, HSMS and SML implemented in Go, for building high-throughput equipment interfaces where a Python event loop would not keep up.
- SECS/GEM overview - Neutral explanation of the message layers and state machines.
- SEMI EDA / Interface A - The E120/E125/ E132/E134 family for equipment data acquisition; how modern fabs get high-rate trace data out of tools for APC and virtual metrology.
- OPC UA for machine-to-machine - Increasingly the integration layer above SECS/GEM in newer facilities and in back-end assembly.
- MST — open-source SECS/GEM driver commentary - Industry perspective on why open equipment integration matters.
- Ignition SECS/GEM module docs - Well-written vendor documentation that doubles as a protocol tutorial.
- Cleanroom classification (ISO 14644) - Particle count classes; ISO 3–5 for lithography areas.
- Airborne molecular contamination - AMC control is a bigger practical constraint than particle count at advanced nodes.
- Fab water and energy use - SEMI's sustainability programme, including the Semiconductor Climate Consortium.
- Fluorinated gas emissions and abatement - EPA partnership data on process gas emissions; the reason cryo etch's lower GWP is a selling point.
- Ultrapure water systems - SEMI F63 and related standards.
- Construction Physics — how fabs get built - Vibration isolation, cleanroom construction sequencing, and why a fab shell costs what it does.
Testing a chiplet stack is harder than testing a die: a bad die found after bonding destroys every good die bonded to it, so known-good-die confidence has to come from pre-bond test that cannot touch final-pitch bonding pads.
- IEEE 1838-2019 — test access for 3D stacked ICs - The primary TAP / secondary TAP / 3D configuration register architecture enabling pre-bond, mid-bond, and post-bond test.
- An inside look at IEEE 1838 - Readable walkthrough of the standard by people who wrote it.
- IEEE 1838 explained for 2.5D/3D/3.5D - Practical framing with the other standards it composes with.
- IEEE 1687 (IJTAG) - Access and control of embedded instruments; the substrate for in-field monitoring in multi-die parts.
- IEEE 1149.1 (JTAG) - Boundary scan; still the foundation everything else hangs off.
- Challenges in testing chiplets - KGD, final test, and system-level test in a heterogeneous stack.
- Testing the stack — DFT for 3D devices - The cost argument, which is usually the deciding one.
- International Test Conference (ITC) - The primary test venue.
- Advantest and Teradyne ATE platforms - Where the economics of test time per device actually get set.
- System-level test - Increasingly mandatory for complex SoCs and stacks that structural test cannot fully cover.
STDF (Standard Test Data Format, SEMI E141) is what ATE actually writes. Nearly all published test analytics work starts by parsing it.
- STDF-Viewer - Free GUI for exploring STDF files: parametric distributions, bin summaries, and wafer maps without writing code.
- pystdf - Python STDF parser; the usual starting point for building a test-data pipeline.
- LinqToStdf - .NET STDF parsing library, for shops built on the Microsoft stack.
- stdf2map - Turns STDF records into wafer bin maps.
- JEDEC JEP122 — failure mechanisms and models - The reference document for BTI, HCI, TDDB, electromigration, and stress migration models.
- IEEE International Reliability Physics Symposium (IRPS) - The venue; the tutorial notes are excellent and often circulated freely.
- Electromigration in advanced interconnects - Why Ru and Mo change the EM picture as much as the resistance picture.
- Bias temperature instability and aging - Aging-aware timing signoff, now standard at advanced nodes.
- Thermomechanical reliability of 3D stacks - ECTC's reliability sessions; TSV Cu pumping, underfill delamination, and bump/hybrid-bond fatigue.
- Moisture, popcorning, and MSL classification (JEDEC J-STD-020) - Assembly-side reliability that becomes harder as packages get larger and thinner.
- Automotive-grade qualification (AEC-Q100) - The stricter regime, now pulling advanced packaging into its scope.
- Trust-Hub - Benchmarks and datasets for hardware Trojan detection, logic locking, and IP protection. The standard evaluation set in the field.
- CAD for Assurance - Tool and dataset index for hardware assurance, including power/EM side-channel datasets for Trojan benchmarks.
- AuthenTree — distributed trust for chiplet systems (arXiv) - MPC-based authentication architecture for heterogeneous chiplet packages.
- Enhancing DFT security in chiplet-based systems (PDF) - The tension between test access and attack surface, which chiplets make worse.
- Benchmarking at the frontier of hardware security — logic locking (arXiv) - Sober assessment of what the benchmarks in this field do and do not prove.
- Trojan Playground — RL for Trojan insertion and detection (arXiv) - Adversarial framing of the detection problem.
- Gate-level information flow tracking (PDF) - Formal approach to detecting information-flow violations from hardware Trojans.
- Securing the silicon supply chain - Industry framing of counterfeit, overproduction, and cloning risk.
- CHES — Cryptographic Hardware and Embedded Systems - The venue for side-channel and fault-injection work.
- HOST — Hardware Oriented Security and Trust - The complementary venue focused on supply chain and assurance.
- SEMI - Equipment billings, Worldwide Fab Forecast, materials market data. The industry's own statistics body.
- SIA — Semiconductor Industry Association - Monthly global billings, the State of the Industry report, and US-centric policy analysis.
- WSTS - The forecast consortium whose numbers the whole industry plans against.
- TechInsights - Teardowns, process analysis, and market data (absorbed the former IC Insights and Strategy Analytics franchises).
- Yole Group - The reference analyst for packaging, MEMS, imaging, and compound semiconductors. Packaging market splits in this list mostly trace back to Yole.
- SemiAnalysis - Deep technical/financial analysis of fabs, packaging capacity, and AI hardware supply chains.
- Counterpoint, TrendForce, Omdia - Supply/demand and pricing tracking, especially for memory and foundry utilization.
- US BIS — export administration regulations and entity list - The primary source. Rules define advanced-node thresholds explicitly (logic at or below 16/14 nm, DRAM at or below 18 nm half-pitch, and NAND layer counts).
- Congressional Research Service — US export controls and China: advanced semiconductors - The best neutral summary of a fast-moving control regime.
- CSIS — semiconductor and AI export control analysis - Focused on allied alignment, which is where the regime's effectiveness is actually determined.
- European Chips Act - Implementation tracking, plus the Chips Act 2.0 proposal adopted in June 2026.
- SEMI Europe policy briefs - Monthly EU policy summaries from the industry association's perspective.
- CHIPS and Science Act — NIST program - US funding programme, including the National Semiconductor Technology Center and the National Advanced Packaging Manufacturing Program.
- NAPMP — National Advanced Packaging Manufacturing Program - Directly relevant if advanced packaging is your area: this is where US public funding is going.
- Japan, Korea, India, and China programme trackers - CSIS and the OECD both maintain comparative subsidy analysis.
- Wafer cost and cost-per-transistor curves - The claim that cost per transistor stopped falling is more nuanced than usually stated; this is where to check it.
- Fab capex per 1,000 wafer starts - Roughly $2–3B per 10k wpm at leading edge, before packaging.
- Mask set costs at advanced nodes - The NRE that makes chiplet reuse economically compelling.
- Chiplet economics - Where disaggregation pays and where it does not.
Process and fabrication
- Microchip Fabrication — Peter Van Zant. The standard novice-to-practitioner guide to the whole process flow, deliberately light on mathematics.
- Fundamentals of Semiconductor Fabrication — Gary May and Simon Sze. Crystal growth, oxidation, lithography, etch, diffusion, implant, deposition, and integration.
- Fundamentals of Semiconductor Manufacturing and Process Control — Gary May and Costas Spanos. The statistics-and-control companion; the best treatment of SPC/APC in a textbook.
- Silicon VLSI Technology — Plummer, Deal, and Griffin. The rigorous process-physics text, with the modeling that underpins TCAD.
- Handbook of Semiconductor Manufacturing Technology — Doering and Nishi. Reference-grade coverage of every module.
Devices and physics
- Physics of Semiconductor Devices — Sze and Ng. The reference.
- Fundamentals of Modern VLSI Devices — Taur and Ning. The scaling-theory text; still the clearest derivation of short-channel effects.
- Nanoscale Transistors — Lundstrom and Guo. The ballistic-transport framing that matters below 10 nm.
Lithography
- Fundamental Principles of Optical Lithography — Chris Mack. The definitive text.
- Field Guide to Optical Lithography — Chris Mack. The condensed version worth keeping on a desk.
- EUV Lithography — Vivek Bakshi (ed.). The reference volume on EUV sources, optics, masks, and resists.
Packaging
- Semiconductor Advanced Packaging — John H. Lau. SiP, fan-in and fan-out WLP/PLP, 2D through 3D integration, chiplet packaging, and bonding methods, with design/materials/process/reliability treated together. The most complete single volume.
- Chiplet Design and Heterogeneous Integration Packaging — John H. Lau. The chiplet-specific companion.
- Semiconductor Packaging: Materials Interaction and Reliability — Andrea Chen and Randy Lo. The materials-interaction view, which is where most packaging failures originate.
- Heterogeneous Integration Roadmap chapters — free, and more current than any book.
Industry and history
- Chip War — Chris Miller. The standard geopolitical history.
- The Chip — T.R. Reid. The invention of the integrated circuit.
- Crystal Fire — Riordan and Hoddeson. The transistor's origin, and the best account of what Bell Labs actually was.
- BookAuthority — semiconductors reading lists - If you want more.
- nanoHUB - Purdue-hosted platform with free courses and runnable simulation tools in the browser. Start with Semiconductor Fundamentals, Fundamentals of Nanotransistors, and Fundamentals of Nanoelectronics.
- MIT OpenCourseWare — Microelectronic Devices and Circuits - Full lecture notes and problem sets.
- Berkeley EE 143 — Microfabrication Technology - Process-focused undergraduate course with public materials.
- Georgia Tech 3D Systems Packaging Research Center - Short courses and research output specifically on packaging.
- imec Academy - Industry training from the research institute itself.
- SEMI University - Workforce-oriented courses on fab operations, equipment, and standards.
- Class Central — semiconductors and microelectronics - Aggregated index of ~300 free and paid courses.
- Zero to ASIC Course - Practical, project-based path from RTL to a real tapeout using the open flow.
- VLSI System Design (VSD) - Large catalogue of hands-on open-EDA and PDK courses.
- Chris Mack's lithography lectures - Free full-length lithography course.
- Asianometry - The best free video explainers on fab technology, equipment history, and industry structure.
- Applied Science - Ben Krasnow builds semiconductor process equipment in a garage; unusually good intuition-builder.
- Sam Zeloof - Homemade integrated circuits, which teaches the process flow better than most courses.
- Breaking Analysis / TechInsights webinars - Teardown-driven technical webinars, often free.
- The Chip Letter podcast and newsletter - History and architecture, well-researched.
- Moore's Lobby / EE podcasts - Interview-format coverage of design and manufacturing.
- Semiconductor Engineering - Free, daily, and technically serious. The single most useful ongoing source for everything in this list.
- SemiAnalysis - Dylan Patel's analysis of fabs, packaging capacity, and AI hardware economics. Some free, most paid.
- Fabricated Knowledge - Doug O'Laughlin on semiconductor companies and cycles from an investment perspective.
- The Asianometry Newsletter - Written companion to the video channel.
- The Chip Letter - Babbage on semiconductor history, architecture, and business strategy.
- Vik's Newsletter - Vikram Sekar; strong on packaging and RF.
- SemiWiki - Long-running community site with EDA and foundry coverage plus active forums.
- 3D InCites - Advanced packaging community and the IFTLE column.
- Semiconductor Digest - Process and materials coverage.
- EE Times - Broad industry news with reliable conference reporting.
- TrendForce Insights - Supply chain and capacity news, fast and frequently first.
- Mark LaPedus on Substack - Veteran process-technology journalist; excellent on device architecture transitions.
| Conference | Focus | When |
|---|---|---|
| IEDM | Devices, process, memory — the flagship | December |
| VLSI Symposium | Technology + circuits, joint | June |
| ISSCC | Solid-state circuits | February |
| SPIE Advanced Lithography + Patterning | Lithography, masks, metrology, resists | February |
| ECTC | Advanced packaging — the flagship | May/June |
| IITC | Interconnect technology | June |
| ASMC | Manufacturing science and fab data | May |
| IRPS | Reliability physics | March/April |
| ITC | Test | Autumn |
| DAC | EDA and design | June/July |
| ICCAD | CAD algorithms | Autumn |
| DATE | Design, automation and test in Europe | Spring |
| ISPD | Physical design | Spring |
| MLCAD | ML for CAD | Autumn |
| Hot Chips | Product architecture disclosures | August |
| SEMICON West / Europa / Taiwan / Korea | Industry + equipment | Various |
| IMAPS Device Packaging | Applied packaging | March |
| Winter Simulation Conference | Fab simulation and scheduling | December |
| AVS ALD/ALE | Atomic layer processes | Summer |
| ASD Workshop | Area-selective deposition | Spring |
- IEEE Transactions on Electron Devices - The device journal.
- IEEE Electron Device Letters - Short-form device results.
- IEEE Transactions on Semiconductor Manufacturing - Fab process control, yield, and metrology. Underused outside industry.
- IEEE Transactions on Components, Packaging and Manufacturing Technology (T-CPMT) - The packaging journal.
- IEEE Transactions on CAD (TCAD) - EDA algorithms.
- Journal of Micro/Nanopatterning, Materials, and Metrology (JM3) - Lithography and patterning.
- Journal of Vacuum Science & Technology A/B - Deposition, etch, and surface science.
- Nature Electronics - High-profile device and materials results.
- ECS Journal of Solid State Science and Technology - Process chemistry.
- r/semiconductors and r/chipdesign — Active practitioner communities.
- SemiWiki forums - Industry veterans, often with first-hand fab and EDA experience.
- Open Source Silicon Slack / FOSSi Foundation - The hub for open hardware and open EDA, including the weekly El Correo Libre newsletter.
- Zero to ASIC community - Practical open tapeout help.
- imec technology forums - ITF conferences, often with public keynote material.
- imec - Leuven. The industry's shared R&D pipeline; every major foundry, equipment vendor, and materials supplier is a partner. Publishes more usable public material than any other institute.
- CEA-Leti - Grenoble. Strong on 3D sequential integration, imaging, and photonics.
- Fraunhofer IZM / IISB / IPMS - Germany. IZM is one of the best public packaging research groups in the world.
- IME A*STAR - Singapore. Advanced packaging, TSV, and hybrid bonding.
- ITRI - Taiwan. The institute TSMC and UMC were spun out of.
- AIST - Japan's national institute of advanced industrial science and technology; its nanoelectronics programmes anchor much of the country's device research.
- Georgia Tech PRC / 3D Systems Packaging - US academic packaging research with strong industry consortium participation.
- SRC — Semiconductor Research Corporation - Consortium funding US academic research; the JUMP 2.0 centers are where a lot of pre-competitive work happens.
- NSTC — National Semiconductor Technology Center - The CHIPS Act R&D entity, operated by Natcast.
- Albany NanoTech / NY CREATES - 300 mm public research fab, IBM's research partner.
- MIT.nano, Stanford SNF, and the NSF National Nanotechnology Coordinated Infrastructure — Open-access cleanrooms; the practical path to running your own process experiments.
- Chalmers, KTH, EPFL, TU Delft, RWTH Aachen - European academic groups with significant device and packaging programmes.
A compact orientation to who does what. Not exhaustive, and market positions change.
| Company | Role | Leading-edge status |
|---|---|---|
| TSMC | Pure-play foundry | N3/N2 in production, A16 with Super Power Rail, A14 targeting High-NA |
| Samsung Foundry | Foundry + IDM | First to GAA at 3 nm; SF2 and below |
| Intel Foundry | IDM + foundry | 18A with RibbonFET + PowerVia; 14A on High-NA |
| Rapidus | Greenfield foundry | 2 nm with IBM/imec, single-wafer flow |
| GlobalFoundries | Foundry | Specialty and mature nodes; exited leading edge |
| SMIC | Foundry | Advanced-node capability constrained by export controls |
| UMC, Tower, Vanguard | Foundry | Specialty and mature |
Samsung, SK hynix, Micron, Kioxia, SanDisk, YMTC, CXMT, Nanya, Winbond
Synopsys, Cadence, Siemens EDA, Ansys (now part of Synopsys), Keysight, Arm, SiFive, Rambus, Alphawave Semi, Zero ASIC
SEMI, JEDEC, IPC, IEEE EPS, IEEE EDS, UCIe Consortium, OCP, OIF, Si2, IRDS
A real fab costs twenty billion dollars. A working transistor costs rather less. This community has demonstrated lithography, deposition, etch, and functional MOSFETs and small ICs on budgets in the thousands — which makes it the only way most people will ever touch process engineering directly. It is also the fastest way to develop intuition for why the real thing is hard.
Hacker Fab — a CMU-originated, multi-university effort to build an open, reproducible "fab in a room" with published designs for every tool in the flow.
- Hacker Fab documentation - The project handbook: process flows, tool build guides, and results. Start here. Licensed CERN-OHL-S.
- Stepper - Maskless DLP photolithography stepper software, the centerpiece tool. Patterns are projected rather than printed on a reticle, which removes the single most expensive item in a garage flow.
- MicroManipulatorStepper - Sub-micrometer 3D motion control platform; the stage that makes alignment and overlay possible.
- Atomic layer deposition tool - Open ALD reactor design.
- Atomic force microscope - Low-cost AFM hardware and firmware, for measuring what you just made.
- RF impedance matcher - Automatic matching network for a sputtering chamber, from the CMU lab.
- Layout tool - PHIDL-based layout generation sized for hobby-scale mask sets.
People and channels
- Sam Zeloof - Made the first homemade lithographically patterned integrated circuits in a garage lab; the Z2 write-ups document the full process flow honestly, including the failures.
- Breaking Taps - Electron microscopy, focused ion beam, and micro-fabrication experiments with unusually careful methodology.
- Applied Science - Ben Krasnow's builds include electron microscopes, vacuum systems, and thin-film deposition from scratch.
- Zero to ASIC Course - The complementary path: rather than building the fab, use a shuttle. See Getting Silicon Made.
Reverse engineering
- SiliconRE - Die traces, reconstructed schematics, and notes on custom chips reverse-engineered from decapped silicon.
- Visual6502 - Polygon-level reconstruction of the 6502 from die photos, simulated transistor by transistor. The original proof that a chip can be fully recovered from its layout.
- Ken Shirriff's blog - Die-photo reverse engineering of analog and digital ICs, explained circuit by circuit.
- awesome-semiconductor-startups - Database of semiconductor startups with technology category, founding year, country, and exits. The list this one is modeled on.
- awesome-opensource-hardware - 300+ open-source hardware tools, generators, and reusable designs.
- awesome-hwd-tools - Open-source hardware design tools with a chip-design focus.
- awesome-hdl - Hardware description languages and the simulation and synthesis tooling around them. Where the RTL material this list omits lives.
- awesome_photonics - Photonic design automation, layout and simulation. Overlaps this list at silicon photonics and co-packaged optics.
- awesome-ai4eda - AI for EDA paper collection.
- awesome-electronics - Broader electronics engineering resources.
- awesome-open-hardware - Open source hardware project practice.
- LLM4ChipDesign - LLM-aided hardware design and verification.
- Semiconductor_Packaging - Packaging workshop material bridging design and assembly.
- Semiconductor-Packaging - Packaging fundamentals notes.
- awesome - The root list, if you need something else entirely.
Contributions are welcome. See CONTRIBUTING.md for the full guidelines; the short version:
- One link, one line, one reason. Every entry needs a description explaining what it is and why someone would open it. "Cool tool" is not a description.
- Prefer primary sources. A vendor technical brief, a standards document, a paper, or a repository beats a news article summarizing one. News articles are fine when they are the only public account of something.
- No dead links, no link farms, no affiliate links, no SEO content pages.
- Keep the sub-10 nm and packaging bias. Excellent resources about 180 nm analog design belong in a different list.
- Say when something is paid or proprietary. This list is not open-source-only, but readers should never be surprised by a paywall.
Open a pull request against README.md, or open an issue if you would rather just suggest
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