🎓 M.Tech Graduate in VLSI Design (2026) from Vellore Institute of Technology (VIT), Chennai.

I am passionate about Analog Layout, Analog/Mixed-Signal IC Design, and Digital IC Design, with hands-on experience in custom analog layout, RTL development, RTL-to-GDSII implementation, and physical verification using industry-standard EDA tools.

I completed an Analog Layout Internship / Training at Semionics using GlobalFoundries 40nm Planar CMOS (GF40) technology, with hands-on exposure to custom analog, mixed-signal, and CMOS circuit layout using Cadence Virtuoso.

During the training, I worked on multiple analog, mixed-signal, and CMOS building blocks, including single-stage and cascode Op-Amps, differential pairs, current mirrors, multi-voltage level shifters, 4/8-bit DACs, band-pass filters, CMOS bandgap references, NMOS clamping circuits, ring oscillators, standard cells, AOI gates, SR latches, D flip-flops, priority encoders, counters, and full adders.

I also have hands-on experience in Analog/RF Circuit Design, Full-Custom Analog Layout, RTL Design, Functional Verification, Logic Synthesis, ASIC Physical Design, Static Timing Analysis (STA), Physical Verification (DRC/LVS), and RC Parasitic Extraction (PEX).

I have worked with multiple CMOS technologies including:

• GlobalFoundries 40nm Planar (GF40)
• TSMC 65nm (Academic)
• SAED32nm
• SCL180nm
• GPDK180nm
• GPDK90nm
• GPDK45nm

🚀 Immediate Joiner | Open to Full-Time Opportunities

🔗 Repository

https://github.com/Rakesh-2306/Semionics-Analog-Layout-Internship-Training

• Technology: GlobalFoundries 40nm Planar CMOS (GF40)
• EDA Tool: Cadence Virtuoso
• Hands-on experience in custom analog, mixed-signal, and CMOS circuit implementation.
• Worked on differential pairs, current mirrors, and passive structures with matching-oriented layout techniques.
• Applied common-centroid, interdigitation, dummy devices, guard rings, shielding, symmetry, and matching-oriented placement.
• Performed manual routing, DRC/LVS, post-layout parasitic extraction (PEX), and layout optimization following foundry design rules.

• Standard Cells
• AOI Gates
• Clocked NOR-Based SR Latch
• CMOS D Flip-Flop
• 8:3 Priority Encoder
• Modulo-8 Counter using JK Flip-Flops
• 4-Bit Full Adder

• Single-Stage Op-Amp
• Cascode Op-Amp
• Multi-Voltage Level Shifter
• 4/8-Bit DACs
• Band-Pass Filter
• CMOS Bandgap Reference
• NMOS Clamping Circuits
• Ring Oscillator

🔗 Repository

https://github.com/Rakesh-2306/Performance-Balanced-Noise-Canceling-Low-Noise-Amplifier

Technology: SCL180nm CMOS

• Designed and analyzed CG-CS, Cascode, and Folded-Cascode LNA architectures using Cadence Virtuoso.
• Performed RF analysis including Gain, Noise Figure, S-Parameters, Linearity (IIP3/OIP3, IMD3, P1dB), and Stability.
• Implemented full-custom analog layout using device matching, common-centroid, guard rings, shielding, and parasitic-aware layout optimization.
• Performed DRC/LVS verification and RC Parasitic Extraction (PEX) following foundry design rules.
• Designed a custom square spiral inductor for RF layout implementation.

🔗 Repository

https://github.com/Rakesh-2306/Ultra-Lightweight-RISC-V-Architecture-for-Anomaly-Detection-in-Healthcare-Application

Technology: SAED32nm

• Designed a custom 3-stage RISC-V processor using Verilog/SystemVerilog.
• Developed RTL modules including ALU, Register File, Control Unit, Immediate Generator, and Pipeline Stages.
• Performed RTL verification using Synopsys VCS.
• Executed synthesis using Synopsys Design Compiler.
• Performed Floorplanning, Placement, CTS, Routing, and Static Timing Analysis (STA) using Synopsys ICC2.

🔗 Repository

https://github.com/Rakesh-2306/Design-and-analysis-of-Low-power-hybrid-full-adder-for-array-multiplier-in-90nm-technology

Technology: GPDK90nm CMOS

• Designed 4-bit and 8-bit Hybrid Full Adder based Array Multipliers.
• Developed schematic and optimized custom layout using Cadence Virtuoso.
• Performed DRC, LVS, and post-layout RC Parasitic Extraction (PEX).
• Evaluated power and delay improvements using post-layout simulations.

• NPTEL — System Design Through Verilog
• NPTEL — VLSI Design Flow: RTL to GDS

💼 Open to Full-Time Opportunities

• 📧 Email: kmrakesh23@gmail.com
• 💼 LinkedIn: https://linkedin.com/in/kmrakesh
• 💻 GitHub: https://github.com/Rakesh-2306