CMOS INVERTER DESIGN USING SKY130-PDK

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📚Contents

1. Tools Used
2. Methodology
3. CMOS Inverter Schematic
4. CMOS Inverter Symbol
5. Testbench for DC and Transient Simulation
6. Simulation Results
   • DC Transfer Characteristics
     • Voltage Transfer Characteristic (VTC)
     • Noise Margin Analysis
   • Transient Analysis
     • Delay Analysis
     • Dynamic Power Analysis
7. CMOS Inverter Layout
8. Layout vs Schematic (LVS)
9. Acknowledgements

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Tools Used

Tool	Purpose
📐 Xschem	Circuit schematic, Symbol creation & SPICE netlist generation
⚙️ Ngspice	DC transfer characteristics, noise margin analysis, transient analysis, delay analysis, power analysis
🧱 Magic	Layout design & physical verification (DRC)
🔗 Netgen	LVS comparison between extracted and schematic netlists

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Methodology

1. 📐 Schematic Design using Xschem

   • CMOS inverter circuit drawn using SKY130 device models
   • Symbol created and testbench constructed from the schematic
   • SPICE netlist generated for simulation

2. ⚙️ Circuit Simulation using Ngspice

   • DC sweep performed to obtain voltage transfer characteristic (VTC)
   • Noise margin calculated from VTC parameters (VIL, VIH, VOL, VOH)
   • Transient switching analysis used to measure propagation delays (tpHL, tpLH)
   • Power analysis performed:
     • Static power from operating point
     • Dynamic power from waveform activity

3. 🧱 Layout Design using Magic

   • Layout created using SKY130 design rules
   • DRC executed to ensure no rule violations

4. 🧾 Extraction

   • Parasitic extraction performed in Magic to generate the extracted netlist

5. 🔗 Layout vs Schematic (LVS) Verification using Netgen

   • Extracted layout netlist compared with schematic netlist
   • LVS matched, confirming correct physical implementation

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CMOS Inverter Schematic

Schematic

CMOS Inverter Symbol

Symbol

Testbench for DC and Transient Simulation

Testbench

Simulation Results

DC Transfer Characteristics

Voltage Transfer Characteristic (VTC)

• The Voltage Transfer Characteristic (VTC) shows the relationship between the output voltage (Vout) and input voltage (Vin).
• It is used to understand how the inverter responds to different input voltage levels.
• VTC is essential for evaluating the switching behavior and performance of the inverter.
• The plot helps identify different operating regions of the CMOS inverter:
  • Cut-off region
  • Transition region
  • Saturation region

Ngspice Console	DC characteristic curve

Noise Margin Analysis

Noise margin quantifies the ability of a CMOS inverter to tolerate noise without logic errors. It is derived from the DC Transfer Characteristic (VTC) and is determined using critical voltage levels:

• VOL = Output LOW level
• VOH = Output HIGH level
• VIH = voltage input high — the minimum voltage needed at the input to be considered logic HIGH (1)
• VIL = voltage input low — the maximum voltage needed at the input to be considered logic LOW (0)

These values are obtained by evaluating the slope of the VTC (gain = |dVout/dVin|).

Ngspice Console	Gain Plot

Note

Measured Values

• VIL ≈ 0.743 V
• VIH ≈ 0.980 V
• VOL ≈ ~0 V
• VOH ≈ ~1.8 V

Noise Margins

• NML = VIL − VOL
• NMH = VOH − VIH

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Transient Analysis

Delay Analysis

Propagation delay describes how long the inverter output takes to respond to an input transition.

• tpHL → Delay during HIGH → LOW transition (output falling)
• tpLH → Delay during LOW → HIGH transition (output rising)
• tp → Average propagation delay ( tp = (tpHL + tpLH) / 2 )

Rise and fall times describe how quickly the output transitions between logic levels:

• tr → Rise time (LOW → HIGH output transition)
• tf → Fall time (HIGH → LOW output transition)

These timing parameters are measured from the transient output waveform using standard percentage definitions:

• Rise time (tr) → Time taken for output to go from 10% to 90% of Vout
• Fall time (tf) → Time taken for output to go from 90% to 10% of Vout
• Propagation delays
  • tpHL → Input: rising 50% point → Output: falling 50% point
  • tpLH → Input: falling 50% point → Output: rising 50% point

Delay Measurement Console	Delay Waveform

Note

Propagation Delays

• tpHL = 0.020498 ns
• tpLH = 0.013525 ns
• tp = 0.017012 ns (average)

Rise / Fall Times

• tr = 0.027106 ns
• tf = 0.030939 ns

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Dynamic Power Analysis

• Dynamic power is consumed only during output switching, when the inverter output transitions between HIGH and LOW.
• A load capacitance (CL) is connected at the inverter output node.
• When VIN is LOW:
  • PMOS is ON, NMOS is OFF
  • VOUT is driven to HIGH (≈ VDD) and CL is charged
• When VIN is HIGH:
  • PMOS is OFF, NMOS is ON
  • VOUT is driven to LOW (≈ 0 V) and CL is discharged
• Each complete charge–discharge cycle consumes energy:
  • E = CL × VDD²
• The average dynamic power is:
  • Pdyn = CL × VDD² × f
• Thus, increasing CL, VDD, or switching frequency f increases dynamic power, while reducing CL an VDD reduces dynamic power under identical conditions.

Power Measurement (Large CL = 0.5 pF)	Power Measurement (Small CL = 0.2 pF)

Dynamic Power Waveform

Load Capacitance	Dynamic Power
0.5 pF	81.48 µW
0.2 pF	32.87 µW

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CMOS Inverter Layout

• The inverter was implemented using Magic VLSI with SKY130 technology.

• Separate PMOS and NMOS transistors were placed in p-well and n-well regions, and metal routing was used to form the output node, VDD and GND connections.

• DRC was performed to ensure layout correctness

• Extraction generated a parasitic-aware netlist

Layout vs Schematic (LVS)

• LVS verification was performed using Netgen to ensure electrical equivalence between the schematic netlist generated from Xschem and the extracted netlist generated from Magic.

• Extracted netlist obtained after layout parasitic extraction

• Netgen compared device connectivity, node names, and parameters

• All connections matched without mismatches

• LVS result: Matched ✔️

Below are the two netlists used for LVS verification:

Extracted Layout Netlist	Schematic Netlist

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Acknowledgements

This project was carried out with the help of teammate:

• Mr. Veeraragavan M – Contributor, Teammate.

The design implements a CMOS inverter using the open-source SKY130 PDK, covering schematic design, SPICE simulation, layout implementation, and DRC/LVS physical verification.