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M extension decoder #274

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57995d1
M extension decoder
tandr3w Aug 14, 2026
94a81c6
avoid repeated instantiation of module
tandr3w Aug 16, 2026
ec4e960
wrap is_mul and is_div in feature flag
tandr3w Aug 16, 2026
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11 changes: 10 additions & 1 deletion Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,10 @@ RISCOF_UTOSS_RISCV_ISA_CONFIG := $(RISCOF_DIR)/utoss_riscv/utoss_riscv_
# =============

UTOSS_RISCV_CONFIG ?= RV32I
UTOSS_RISCV_ENABLE_MUL ?= $(if $(findstring M,$(UTOSS_RISCV_CONFIG)),1,0)
UTOSS_RISCV_ENABLE_DIV ?= $(if $(findstring M,$(UTOSS_RISCV_CONFIG)),1,0)
UTOSS_RISCV_ENABLE_M := $(if $(filter 1 1,$(UTOSS_RISCV_ENABLE_MUL) $(UTOSS_RISCV_ENABLE_DIV)),1,0)
UTOSS_RISCV_ANY_M := $(if $(filter 1,$(UTOSS_RISCV_ENABLE_MUL) $(UTOSS_RISCV_ENABLE_DIV)),1,0)

UTOSS_BOOT_ADDR ?= 32\'h0000_0000

Expand All @@ -44,7 +48,12 @@ ifneq ($(findstring A,$(UTOSS_RISCV_CONFIG)),)
MISA_VALUE := $(shell printf "0x%x" $$(( $(MISA_VALUE) | 0x1 )))
endif

UTOSS_RISCV_VERILATOR_DEFINES := $(if $(findstring B,$(UTOSS_RISCV_CONFIG)),-DUTOSS_RISCV_ENABLE_B_EXT)
UTOSS_RISCV_VERILATOR_DEFINES := \
$(if $(findstring B,$(UTOSS_RISCV_CONFIG)),-DUTOSS_RISCV_ENABLE_B_EXT) \
$(if $(filter 1,$(UTOSS_RISCV_ENABLE_M)),-DUTOSS_RISCV__M_ENABLED) \
$(if $(filter 1,$(UTOSS_RISCV_ENABLE_MUL)),-DUTOSS_RISCV__MUL_ENABLED) \
$(if $(filter 1,$(UTOSS_RISCV_ENABLE_DIV)),-DUTOSS_RISCV__DIV_ENABLED) \
$(if $(filter 1,$(UTOSS_RISCV_ANY_M)),-DUTOSS_RISCV__ANY_M)
UTOSS_RISCV_RISCOF_VERILATOR_DEFINES := -DUTOSS_PIPELINE_LOGGER

# ===========================
Expand Down
49 changes: 49 additions & 0 deletions src/ext/m/decoder.sv
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Original file line number Diff line number Diff line change
@@ -0,0 +1,49 @@
`include "src/timescale.svh"
`include "src/headers/types.svh"
`include "src/ext/m/types.svh"

/* verilator lint_off DECLFILENAME */
module ext__m__decoder
/* verilator lint_on DECLFILENAME */
( input [2:0] funct3
, input [6:0] funct7
, input opcode_t opcode
, output logic is_mul
, output logic is_div
`ifdef UTOSS_RISCV__MUL_ENABLED
, output ext__m__types::m_mul_control_t mul_control
`endif
`ifdef UTOSS_RISCV__DIV_ENABLED
, output ext__m__types::m_div_control_t div_control
`endif
);

always @(*) begin
is_mul = 1'b0;
is_div = 1'b0;
`ifdef UTOSS_RISCV__MUL_ENABLED
mul_control = ext__m__types::M_ALU_CTRL__MUL_NONE;
`endif
`ifdef UTOSS_RISCV__DIV_ENABLED
div_control = ext__m__types::M_ALU_CTRL__DIV_NONE;
`endif

if (opcode == OPCODE_OP && funct7 == 7'b0000001) begin
case (funct3)
`ifdef UTOSS_RISCV__MUL_ENABLED
3'b000: begin is_mul = 1'b1; mul_control = ext__m__types::M_ALU_CTRL__MUL; end
3'b001: begin is_mul = 1'b1; mul_control = ext__m__types::M_ALU_CTRL__MULH; end
3'b010: begin is_mul = 1'b1; mul_control = ext__m__types::M_ALU_CTRL__MULHSU; end
3'b011: begin is_mul = 1'b1; mul_control = ext__m__types::M_ALU_CTRL__MULHU; end
`endif
`ifdef UTOSS_RISCV__DIV_ENABLED
3'b100: begin is_div = 1'b1; div_control = ext__m__types::M_ALU_CTRL__DIV; end
3'b101: begin is_div = 1'b1; div_control = ext__m__types::M_ALU_CTRL__DIVU; end
3'b110: begin is_div = 1'b1; div_control = ext__m__types::M_ALU_CTRL__REM; end
3'b111: begin is_div = 1'b1; div_control = ext__m__types::M_ALU_CTRL__REMU; end
`endif
default:;
endcase
end
end
endmodule
27 changes: 27 additions & 0 deletions src/ext/m/types.svh
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@@ -0,0 +1,27 @@
`ifndef EXT__M__TYPES
`define EXT__M__TYPES

/* verilator lint_off DECLFILENAME */
package ext__m__types;
/* verilator lint_on DECLFILENAME */
typedef enum logic [2:0]
{
M_ALU_CTRL__MUL_NONE = 3'b000
, M_ALU_CTRL__MUL = 3'b001
, M_ALU_CTRL__MULH = 3'b010
, M_ALU_CTRL__MULHSU = 3'b011
, M_ALU_CTRL__MULHU = 3'b100
} m_mul_control_t;

typedef enum logic [2:0]
{
M_ALU_CTRL__DIV_NONE = 3'b000
, M_ALU_CTRL__DIV = 3'b001
, M_ALU_CTRL__DIVU = 3'b010
, M_ALU_CTRL__REM = 3'b011
, M_ALU_CTRL__REMU = 3'b100
} m_div_control_t;

endpackage

`endif
8 changes: 8 additions & 0 deletions src/interfaces/id_to_ex_if.svh
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Expand Up @@ -26,6 +26,14 @@ typedef struct packed {
`ifdef UTOSS_RISCV_ENABLE_B_EXT
ext__b__types::b_alu_control_t b_alu_control;
`endif
`ifdef UTOSS_RISCV__MUL_ENABLED
logic is_mul;
ext__m__types::m_mul_control_t mul_control;
`endif
`ifdef UTOSS_RISCV__DIV_ENABLED
logic is_div;
ext__m__types::m_div_control_t div_control;
`endif
} id_to_ex_t;

`endif
28 changes: 28 additions & 0 deletions src/modules/Instruction_Decode/Instruction_Decode.sv
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Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
`include "src/headers/params.svh"
`include "src/headers/types.svh"
`include "src/ext/m/types.svh"
`include "src/timescale.svh"

module Instruction_Decode
Expand All @@ -14,6 +15,16 @@ module Instruction_Decode
`ifdef UTOSS_RISCV_ENABLE_B_EXT
, output ext__b__types::b_alu_control_t b_alu_control
`endif

`ifdef UTOSS_RISCV__MUL_ENABLED
, output logic is_mul
, output ext__m__types::m_mul_control_t mul_control
`endif
`ifdef UTOSS_RISCV__DIV_ENABLED
, output logic is_div
, output ext__m__types::m_div_control_t div_control
`endif

);

alu_op_t alu_op;
Expand Down Expand Up @@ -155,4 +166,21 @@ module Instruction_Decode
);
`endif

`ifdef UTOSS_RISCV__ANY_M
ext__m__decoder u_ext__m__decoder
( .funct3 ( funct3 )
, .funct7 ( funct7 )
, .opcode ( opcode )
, .is_mul ( is_mul )
, .is_div ( is_div )
`ifdef UTOSS_RISCV__MUL_ENABLED
, .mul_control ( mul_control )
`endif
`ifdef UTOSS_RISCV__DIV_ENABLED
, .div_control ( div_control )
`endif
);
`endif


endmodule
29 changes: 29 additions & 0 deletions src/stages/decode_stage.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,15 @@ module decode_stage
alu_src_b_t cfsm__alu_src_b;

alu_control_t alu_control;

`ifdef UTOSS_RISCV__MUL_ENABLED
logic is_mul;
ext__m__types::m_mul_control_t mul_control;
`endif
`ifdef UTOSS_RISCV__DIV_ENABLED
logic is_div;
ext__m__types::m_div_control_t div_control;
`endif
`ifdef UTOSS_RISCV_ENABLE_B_EXT
ext__b__types::b_alu_control_t b_alu_control; //NEW
`endif
Expand Down Expand Up @@ -71,6 +80,18 @@ module decode_stage
, .rd ( rd )
, .rs1 ( rs1 )
, .rs2 ( rs2 )
`ifdef UTOSS_RISCV__MUL_ENABLED
, .is_mul ( is_mul )
`endif
`ifdef UTOSS_RISCV__DIV_ENABLED
, .is_div ( is_div )
`endif
`ifdef UTOSS_RISCV__MUL_ENABLED
, .mul_control ( mul_control )
`endif
`ifdef UTOSS_RISCV__DIV_ENABLED
, .div_control ( div_control )
`endif
`ifdef UTOSS_RISCV_ENABLE_B_EXT
, .b_alu_control ( b_alu_control )
`endif
Expand Down Expand Up @@ -121,6 +142,14 @@ module decode_stage
assign id_to_ex.imm_ext = imm_ext;
assign id_to_ex.pc_cur = if_to_id.pc_cur;
assign id_to_ex.pc_plus_4 = if_to_id.pc_plus_4;
`ifdef UTOSS_RISCV__MUL_ENABLED
assign id_to_ex.is_mul = is_mul;
assign id_to_ex.mul_control = mul_control;
`endif
`ifdef UTOSS_RISCV__DIV_ENABLED
assign id_to_ex.is_div = is_div;
assign id_to_ex.div_control = div_control;
`endif
`ifdef UTOSS_RISCV_ENABLE_B_EXT
assign id_to_ex.b_alu_control = b_alu_control;
`endif
Expand Down
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