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VRM21-Studios/README.md

Hi there, I'm Ryadh 👋

Welcome to VRM21 Studios — Versatile Reconfigurable Modules

Vision, Rêve, Magie ✨

I am an Electrical Engineering graduate specializing in Digital IC Design, RTL Engineering, and Hardware-Software Co-Design. I am passionate about bridging the gap between low-level hardware architecture and high-level software control.

🛠️ Core Focus

  • Digital IC & RTL Design: Writing highly optimized, reusable Verilog for FPGAs.
  • Computer Architecture: Custom RV32I RISC-V cores and AXI4/AXI-Stream interfaces.
  • Hardware Acceleration: High-performance Audio DSP pipelines (QMF, FIR/IIR filters, Spatial Audio, Spectral Processing) and AI architectures, including Spiking Neural Networks (SNNs) and Systolic Arrays.
  • HW/SW Co-Design: Utilizing Xilinx Vivado, Vitis, and the Python PYNQ framework for seamless IP control across platforms like Zynq UltraScale+, Kria KV260, and KR260.

📈 Highlighted Expertise

My capstone and independent research heavily involve Xilinx adaptive SoCs. I have architected the VRM Series SoC—a system utilizing a custom RISC-V CPU to orchestrate complex DSP hardware accelerators.

True to its origins in Voix, Rythme, Musique, my pinned repositories feature reference RTL implementations of various audio DSP nodes. These modules are designed with maximum flexibility in mind, ready to be reconfigured for diverse applications.

🌱 Current Endeavors

  • Expanding my knowledge footprint into Data Science and Machine Learning to further complement custom hardware AI accelerators.
  • Preparing and structuring robust RTL architectures for academic research and manuscript publications.

📫 Reach me at: LinkedIn | Email | ORCID: 0009-0000-2759-2235

Pinned Loading

  1. FIR-Module-FPGA FIR-Module-FPGA Public

    A FIR filter for 16-bit stereo PCM audio DSP implemented on an FPGA with fixed-point representation.

    Verilog 1 1

  2. Audio-Gain-Module-FPGA Audio-Gain-Module-FPGA Public

    Reference RTL implementation of a stereo gain stage, showcasing fixed-point DSP decisions and AXI integration on FPGA.

    Verilog

  3. IIR-1st-Order-Module-FPGA IIR-1st-Order-Module-FPGA Public

    A first-order IIR filter for 16-bit PCM stereo data implemented on an FPGA with fixed-point representation.

    Verilog

  4. Mid-Side-Transform-Module-FPGA Mid-Side-Transform-Module-FPGA Public

    Mid-Side transform RTL (encoder/decoder) in Verilog with AXI-Stream and AXI-Lite control, verified via cycle-accurate simulation on KV260.

    Verilog

  5. Non-Linear-Distortion-Module-FPGA Non-Linear-Distortion-Module-FPGA Public

    A deterministic, fixed-latency tanh non-linear distortion DSP block implemented in Verilog and integrated with AXI-Stream, published as a reference RTL design.

    Verilog 1

  6. Simple-Delay-Module-FPGA Simple-Delay-Module-FPGA Public

    AXI4-Stream stereo audio delay implemented on FPGA, using BRAM-based circular buffers and AXI-Lite control.

    Verilog