A couple of bucks

FPGAs are frequently used to control power electronic circuits. More often than not, the power circuit is excluded from the FPGA test benches because it is difficult to model circuits in standard VHDL or Verilog. There is an Analog and Mixed-Signal (AMS) extension for this, but few are using that.

This repo demonstrates how to model a power circuit in standard VHDL that enables the test bench to perform mixed-signal simulations. The example circuit is a DC/DC converter (or Buck converter) with the regulator implemented in an FPGA. The VHDL test bench verifies the operation in closed loop, allowing the regulator parameters to be fine-tuned.

Buck converter

The circuit diagram of a synchronous buck converter is shown below:

The circuit consists of two MOSFETs in a half-bridge configuration, an inductor and a capacitor. The output voltage is given by: $V_{out}=D*V_{in}, D \in (0,1)$ where D is the duty cycle of the PWM input.

Buck converter modeling

The MOSFET transistors are modelled as on/off switches, and with two inputs we can analyze the circuit in four different stages. Circuit analysis is done by applying Kirchhoff's circuit laws (sum of currents and sum of voltages), plus the current-voltage relationship of an inductor ($V(t)=L\frac{dI(t)}{dt}$) and a capacitor ($I(t)=C\frac{dV(t)}{dt}$). From this we get a set of ordinary differential equations. These are solved numerically using Eulers method. See ¹ for example equations.

Stage 1

The high-side MOSFET transistor is on, low-side is off. Current is drawn from the Vin supply.

Stage 2

The low-side MOSFET transistor is on, high-side is off.

Stage 3

Both MOSFETs are off. The body-diode of the low-side MOSFET allows current to flow through the inductor.

Stage 4

When both transistors are on, the power supply is short circuited! There is no point modelling this stage, but the model will check for this condition and throw a failure if it occurs.

VHDL testbench

The test bench contains both the FPGA logic and buck converter circuit. The buck regulator is typically part of a larger FPGA design. The feedback signal is the output voltage, which is digitized by an ADC converter. The ADC interface is SPI.

The input voltage to the converter is 15V, and the setpoint is 9V. The feedback voltage is scaled down to the input range of the ADC (2.5V). The circuit can also operate in current mode. The feedback signal is then derived from a small sense resistor in series with the load. The FPGA clock frequency is 48MHz, and the PWM resolution is set to 7bit. This gives a regulator loop frequency of $Reg_{freq}=\frac{48Mhz}{2^7}=375kHz$.

LTspice model

The LTspice model of the buck converter is shown below. The main difference from the VHDL circuit model is that a proper transistor spice model is used (a gate driver is thus needed). The regulator is mostly analog as well, but all parameters are the same. The circuit and regulator parameters in the LTspice model have the same names as in the VHDL code. This makes it easy to automatically update the LTspice model with the parameters defined in the VHDL packages.

Simulation result

The simulation result of the startup transient (2ms soft-start) and 1A load step (at 3ms) is shown below (after regulator tuning). Very good match between the VHDL model and LTspice model.

References

Footnotes

1. Signals 2022-3: “Using Python for the Simulation of a Closed-Loop PI Controller for a Buck Converter” ↩