net: sparx5: fix setup of AGGR_CFG registers on sparx5 - #23
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There are some issues with how the current implementation sets up the aggregation configuration registers for the sparx5. Firstly, lag_mask is initialised with DECLARE_BITMAP which will initialise it as an array of longs (64-bits). Since there are 65 sparx5 ports, there will be two longs in the array, with the second one only covering the 65th port. This means the mask in the writes to ANA_AC_AGGR_CFGx will only be correct for the first 32 ports. Secondly, the current implementation writes lag_mask[1] to ANA_AC_AGGR_CFG again. It was likely meant to be ANA_AC_AGGR_CFG1, but as mentioned earlier, it wouldn't have been writing the correct bits without the above fix. Signed-off-by: Connor Myers <connor.myers@digi.com>
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There are some issues with how the current implementation sets up the aggregation configuration registers for the sparx5.
Firstly, lag_mask is initialised with DECLARE_BITMAP which will initialise it as an array of longs (64-bits). Since there are 65 sparx5 ports, there will be two longs in the array, with the second one only covering the 65th port. This means the mask in the writes to ANA_AC_AGGR_CFGx will only be correct for the first 32 ports.
Secondly, the current implementation writes lag_mask[1] to ANA_AC_AGGR_CFG again. It was likely meant to be ANA_AC_AGGR_CFG1, but as mentioned earlier, it wouldn't have been writing the correct bits without the above fix.