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@uoftasic University of Toronto - ASIC Team

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    24 repositories

    • ic101

      Public
      Python
      •
      MIT License
      •0•0•0•1•Updated Aug 27, 2026Aug 27, 2026

    • workspace

      Public
      Shell
      •0•0•0•0•Updated Aug 27, 2026Aug 27, 2026

    • ad101

      Public
      AD101 — Signals | Signals in time and frequency: waveforms, spectra, and Bode plots.
      Python
      •
      MIT License
      •0•0•0•0•Updated Aug 27, 2026Aug 27, 2026

    • dd103

      Public
      DD103 — RTL on FPGAs & ASICs. SystemVerilog in depth, and how the same RTL lowers differently to FPGA and ASIC. UofT ASIC internal education.
      SystemVerilog
      •
      MIT License
      •0•0•0•0•Updated Aug 26, 2026Aug 26, 2026

    • ad103

      Public
      AD103 — Nonlinear Circuits. The diode and the MOSFET in XSchem: regions of operation, and what the parameters mean. UofT ASIC internal education.
      Python
      •
      MIT License
      •0•0•0•0•Updated Aug 26, 2026Aug 26, 2026

    • edu

      Public
      The primary repo to host the educational material made by the UofT ASIC Team
      Python
      •0•0•0•1•Updated Aug 26, 2026Aug 26, 2026

    • dd102

      Public
      DD102 — Digital Logic & FPGAs. Draw a circuit, transcribe it to SystemVerilog, and run it on an FPGA. UofT ASIC internal education.
      SystemVerilog
      •
      MIT License
      •0•0•0•0•Updated Aug 26, 2026Aug 26, 2026

    • dd101

      Public
      DD101 — Intro to Digital Logic. Logic from first principles: yes/no, gates, and how they compose into anything. UofT ASIC internal education.
      HTML
      •
      MIT License
      •0•0•0•0•Updated Aug 26, 2026Aug 26, 2026

    • dd104

      Public
      DD104 — Pre-Silicon Verification. Verilator and cocotb: find the bugs hiding in a real 8-bit core. UofT ASIC internal education.
      Python
      •
      MIT License
      •0•0•0•0•Updated Aug 26, 2026Aug 26, 2026

    • ad104

      Public
      AD104 — Layout. UofT ASIC internal education.
      Python
      •
      MIT License
      •0•0•0•0•Updated Aug 26, 2026Aug 26, 2026

    • ad102

      Public
      AD102 — Linear Circuits & Fabrication. Linear analysis, folded together with how passives are actually built on a chip. UofT ASIC internal education.
      Python
      •
      MIT License
      •0•0•0•0•Updated Aug 26, 2026Aug 26, 2026

    • librelane-action

      Public
      Harden a design to GDSII in GitHub Actions. Course CI for the UofT ASIC education initiative.
      Python
      •0•0•0•0•Updated Aug 26, 2026Aug 26, 2026

    • uoftasic.github.io

      Public
      Project Team portfolio website
      SCSS
      •0•0•0•0•Updated Aug 21, 2026Aug 21, 2026

    • ece334-docs

      Public
      TeX
      •0•0•0•0•Updated Aug 19, 2026Aug 19, 2026

    • ece334-labs

      Public
      Python
      •0•0•1•0•Updated Aug 19, 2026Aug 19, 2026

    • ece334

      Public
      Python
      •
      MIT License
      •0•0•0•0•Updated Aug 3, 2026Aug 3, 2026

    • course-template

      Public template
      The template repository for the UofT ASIC internal education modules
      Python
      •
      MIT License
      •0•0•0•0•Updated Jul 28, 2026Jul 28, 2026

    • .github

      Public
      0•0•0•0•Updated Jun 6, 2026Jun 6, 2026

    • ttsky-verilog-tinyCGRA

      Public
      SystemVerilog
      •
      Apache License 2.0
      •0•0•0•0•Updated May 18, 2026May 18, 2026

    • pcs-link-controller-lite

      Public
      Verilog
      •
      Apache License 2.0
      •1•0•0•0•Updated May 9, 2026May 9, 2026

    • IC-Hackathon-FPGA-Template

      Public template
      SystemVerilog
      •0•0•0•0•Updated Feb 14, 2026Feb 14, 2026

    • modelsim-docker

      Public
      An attempt at creating a docker image for modelsim & quartus verification
      0•0•0•0•Updated Feb 11, 2026Feb 11, 2026

    • ethrodite

      Public
      SystemVerilog
      •
      Apache License 2.0
      •0•0•0•0•Updated Nov 10, 2025Nov 10, 2025

    • simproc

      Public
      SimpleProcessor, taped out on TTSky25b
      asicprocessorsky130
      asicprocessorsky130
      SystemVerilog
      •
      Apache License 2.0
      •1•0•0•1•Updated Nov 10, 2025Nov 10, 2025
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