🔗 Repository:

 **Half Adder** – Schematic to GDSII

 

This repository showcases the complete custom digital design flow of a Half Adder, from schematic capture to final GDSII layout. The design is implemented using standard cells or transistor-level design techniques, with optimization for area and performance.

**🧩 Key Highlights:**

• Custom schematic design of a Half Adder
• Symbol creation and hierarchy management
• Layout design with DRC and LVS verification
• Parasitic extraction (PEX) to analyze layout-induced effects
• Post-layout simulation to validate performance under realistic conditions
• Final GDSII file ready for tape-out or further integration

**💡 Design Specs:**

• Technology node: (specify if used, e.g., 45nm, 180nm)
• Compact and optimized transistor sizing
• DRC & LVS clean using Cadence tools or equivalent
• Includes performance insights due to parasitic components

**🚀 Purpose:**

• Educational demonstration of the full custom VLSI flow
• Serves as a reference for learning schematic vs layout comparison
• Foundational IP block for arithmetic logic units (ALUs)