Fix POWER7 build: correct AltiVec version guards for POWER8-only intrinsics - #1414
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FYI @fo40225 ; using gcc-15 + power9 causes a few test errors: https://github.com/simd-everywhere/simde/actions/runs/30464647634/job/90619226190?pr=1414 And |
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…4.1) x86/sse2: require POWER8 for vec_float2 in simde_mm_cvtpd_ps GCC only provides vec_float2 with -mcpu=power8 or later; building with -mcpu=power7 fails with: error: '__builtin_vsx_float2_v2df' requires the '-mcpu=power8' and '-mvsx' options Raise the guard from SIMDE_POWER_ALTIVEC_P7_NATIVE to SIMDE_POWER_ALTIVEC_P8_NATIVE so POWER7 falls back to the portable implementation. x86/sse4.1: require POWER8 for 64-bit vec_cmpeq in simde_mm_cmpeq_epi64 vec_cmpeq on vector long long maps to vcmpequd, a POWER8 (ISA 2.07) instruction. GCC rejects it below power8: error: '__builtin_altivec_vcmpequd' requires the '-mcpu=power8' and '-mvsx' options The previous SIMDE_POWER_ALTIVEC_P6_NATIVE guard was doubly wrong: POWER6 does not even have the vector long long type. Raise the guard to SIMDE_POWER_ALTIVEC_P8_NATIVE.
All existing PowerPC CI configurations target power8 or later, so the "SIMDE_POWER_ALTIVEC_P7_NATIVE without P8_NATIVE" configuration was never exercised, allowing POWER8-only intrinsics behind P6/P7 guards (fixed in the previous commit) to slip through. Build with -mcpu=power7 -Wextra -Werror so any use of a POWER8-only intrinsic under a P6/P7 guard fails the build, and run the test suite under QEMU. The exe_wrapper uses -cpu power9 because Ubuntu's ppc64el userspace has a POWER8 baseline; power7-targeted code is a subset ISA and runs fine on the newer CPU model.
simde_vpaddlq_s32() and simde_vpaddlq_u32() in paddl.h use vec_add() on 64-bit integer vectors via vec_mule()/vec_mulo() with int32 operands. The underlying GCC builtins (vaddudm, vmulesw, vmulosw, vmuleuw, vmulouw) are POWER8 VSX instructions, not available on POWER7. Change the guard from SIMDE_POWER_ALTIVEC_P7_NATIVE to SIMDE_POWER_ALTIVEC_P8_NATIVE so these paths are only used when targeting POWER8 or later.
Five functions in wasm/simd128.h use SIMDE_POWER_ALTIVEC_P7_NATIVE to guard code paths that emit 64-bit integer SIMD operations: - simde_wasm_i64x2_all_true(): vec_all_ne on int64 (vcmpequd_p) - simde_wasm_i32x4_extend_low_i16x8(): vec_sra on long long (vsrad) - simde_wasm_i32x4_extend_high_i16x8(): vec_sra on long long (vsrad) - simde_wasm_i64x2_extmul_low_i32x4(): vec_mule producing int64 - simde_wasm_i64x2_extmul_high_i32x4(): vec_mule producing int64 - simde_wasm_u64x2_extmul_low_u32x4(): vec_mule producing uint64 - simde_wasm_u64x2_extmul_high_u32x4(): vec_mule producing uint64 All of these require POWER8. The extmul functions additionally cause a GCC 14 internal compiler error (ICE at optabs.cc:326) when compiled with -mcpu=power7, because the compiler attempts to expand a widen-multiply pattern that has no POWER7 implementation. Change all guards from P7_NATIVE to P8_NATIVE. For the extmul_low signed/unsigned variants, also collapse the now-redundant inner P8/P7 branch (the outer guard already guarantees P8).
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I'm not sure how to adjust the CI for Clang 18 to 21 when treating warnings as errors on CPUs that support AVX10.1-512. |
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Summary
SIMDE_POWER_ALTIVEC_P7_NATIVEguards that protect 64-bit integer AltiVec/VSX operations across four files (sse2.h,sse4.1.h,neon/paddl.h,wasm/simd128.h).All affected operations require POWER8 and fail to compile or trigger a GCC 14 ICE when targeting POWER7.
power7(GCC 14,-mcpu=power7) cross-compilation job to thegcc-qemuCI matrix to prevent future regressions.Background
POWER7 introduced AltiVec (VMX) with 8/16/32-bit integer SIMD, but 64-bit integer vector operations (
vaddudm,vsrad,vmulesw,vcmpequd, etc.) were added in POWER8 as part of VSX.SIMDe's
SIMDE_POWER_ALTIVEC_P7_NATIVEmacro maps to POWER7 AltiVec availability, so code behind this guard must not use 64-bit integer vector builtins.Files Changed
simde/x86/sse2.hvec_add/vec_cmpeq/vec_cmpgt/vec_sl/vec_sr/vec_sraon int64simde/x86/sse4.1.hvec_cmpeqon int64simde/arm/neon/paddl.hvec_add/vec_mule/vec_muloon int64simde/wasm/simd128.hvec_all_ne/vec_sra/vec_muleon int64.github/workflows/ci.yml