lvs-calibre

Here are 2 public repositories matching this topic...

rohaansch / netlist-parser

A pure-Python parser for SPICE, Spectre, CDL, and DSPF netlist files — extracts subcircuit, port, device, and parasitic data for EDA automation and library characterization workflows.

parser simulation eda spice characterization spectre vlsi netlist semiconductor cdl lvs parasitic vlsi-design dspf lvs-calibre

Updated Apr 3, 2026
Python

SeanS4 / riscv-asic-physical-design

Star

32-bit RISC-V ASIC physical design featuring a custom standard cell library, bit-sliced datapath routed in Cadence Virtuoso, and automated Cadence Innovus implementation.

asic computer-architecture vlsi risc-v cadence-virtuoso drc tcl-scripts physical-design place-and-route freepdk45 cadence-innovus standard-cells cmos-logic lvs-calibre

Updated Aug 13, 2026
Tcl

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