c4o-core (ChipForAll Engine)

c4o-core is the underlying EDA toolchain engine for the ChipForAll project. It packages open-source silicon tools into a unified, Python-driven Docker container.

Note: If you are a beginner, please use the ChipForAll Template instead of using this engine directly.

🚀 Quick Start

You can run c4o-core directly via Docker. Mount your current directory ($(PWD)) to /workspace (or any workspace path) to persist artifacts.

docker run --rm -v $(PWD):/workspace -w /workspace ghcr.io/anlit75/c4o-core:latest <command>

🛠 Command Reference

The engine supports the following commands via its Python entrypoint:

Command	Description
lint	Runs Verilator linting checks on RTL_FILES.
sim	Compiles and runs simulation using Icarus Verilog on RTL_FILES + TEST_FILES.
synth	Performs logic synthesis using Yosys on RTL_FILES only. Generates build/synthesis.json.
pdk	Installs/Enables the Sky130 PDK via Volare into ./pdks.
gds	Validates configuration for OpenLane flow (pre-flight check). Requires valid RTL_FILES.

⚙️ Configuration (config.json)

c4o-core looks for a config.json file in your workspace to understand your design structure.

Minimal Example (RTL Only)

Supports Glob Patterns! You can match all files in a directory recursively using **/*.v.

{
  "DESIGN_NAME": "counter",
  "RTL_FILES": ["src/**/*.v"],
  "TEST_FILES": ["test/*.v"]
}

Advanced Example (Complex Projects)

For projects with many files and header includes (e.g., `include "defines.vh").

{
  "DESIGN_NAME": "cpu_top",
  "RTL_FILES": [
    "src/core/**/*.v",
    "src/peripherals/*.v",
    "src/top.v"
  ],
  "TEST_FILES": ["test/tb_top.v"],
  "INCLUDE_DIRS": ["src/include", "src/core/include"]
}

Full Example (RTL + GDS)

Required for make gds / OpenLane flow.

{
  "DESIGN_NAME": "counter",
  "RTL_FILES": ["src/counter.v", "src/alu.v"],
  "TEST_FILES": ["test/tb_counter.v"],
  "INCLUDE_DIRS": ["src/include"],
  "PDK": "sky130A",
  "STD_CELL_LIBRARY": "sky130_fd_sc_hd",
  "DIE_AREA": "0 0 100 100",
  "FP_CORE_UTIL": 40,
  "FP_SIZING": "absolute",
  "CLOCK_PORT": "clk",
  "CLOCK_PERIOD": 10.0
}

Key Configuration Options

• RTL_FILES: List of synthesizable Verilog source files. Supports glob patterns (e.g., src/**/*.v).
  • Note: The legacy VERILOG_FILES key is supported for backward compatibility but is deprecated.
• TEST_FILES: List of simulation testbench files (non-synthesizable). Supports glob patterns.
• INCLUDE_DIRS: List of directories containing Verilog include files (.vh, .h).
• DESIGN_NAME: Top-level module name for synthesis.

🏗 Architecture

• System Path: The EDA tools and python scripts are installed in /opt/c4o-core.
• User Path: Users should mount their workspace to /workspace.
• PDK Path: The pdk command installs artifacts into the user's volume (./pdks), ensuring persistence across container runs.

📦 Included Tools

• Yosys: Open Synthesis Suite
• Verilator: High-performance Verilog simulator/linter
• Icarus Verilog: Verilog simulation and synthesis tool
• Volare: PDK Version Manager
• Cocotb: Coroutine based cosimulation library

License

This project is licensed under the Apache License 2.0 - see the LICENSE file for details.

Note: This framework invokes various third-party open-source EDA tools (Yosys, Verilator, OpenLane, etc.), which are distributed under their respective licenses.