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rtl-to-gdsii

Here are 32 public repositories matching this topic...

ramiomer94 / VLSI-design-projects

This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.

verilog semiconductor-physics genus custom-layout virtuoso digital-logic-design static-timing-analysis vlsi-design asic-design rtl-design innovus standard-cells eda-tools rtl-verification cmos-design rtl-to-gdsii cadence-tools

Updated Jul 12, 2025
Verilog

Ammar-Wahidi / NPU

Silicon-proven INT8 systolic NPU (8×8 MAC array) taped out on SkyWater 130nm via LibreLane. Features a custom 32-bit ISA, UART–APB host interface, and fused streaming datapath. Validated on chest X-ray pneumonia detection. Silicon Sprint 2026 — AUC.

tapeout systolic-arrays npu openroad edge-ai asic-design medical-ai int8-quantization digital-ic-design librelane rtl-to-gdsii skywater-130nm

Updated May 24, 2026
Verilog

BinatM / Neural-Engine

SPEAR – Single Neuron Hardware Accelerator Engine. A collaborative hardware project combining full custom ASIC design and FPGA-based validation. The CHIP team designed a perceptron accelerator from RTL to GDSII using Synopsys tools and TSMC 28nm. The FPGA team built a working test platform on DE10-Lite. Developed with mentorship and technical suppo

asic fpga neural-network hardware verification rtl chip perceptron vlsi gdsii physical-design rtl-to-gdsii

Updated Aug 1, 2025

vyges-tools / vybox-eda

Clean-room container for building RTL → GDSII: a slim, pinned open-source EDA toolchain (Yosys · Verilator · OpenROAD · Magic · KLayout · Netgen · ngspice + sky130/gf180 PDKs), built from scratch on GitHub Actions and published to GHCR.

Updated Aug 5, 2026
Dockerfile

RAMA-L7 / vlsi-pd-staff-engineer

Multi-agent framework for RTL-to-GDSII physical design using Claude Code — 9 specialized agents, stage-gate verification, and forensic ECO debugging on Yosys + OpenROAD + Sky130

eda multi-agent vlsi yosys physical-design openroad asic-design sky130 claude-code rtl-to-gdsii

Updated May 14, 2026
Shell

shri-at / CNNaccelerator

CNN accelerator datapath components

verilog vlsi cnn-accelerator rtl-to-gdsii

Updated Jan 5, 2026
Verilog

configurable-cache-memory-subsystem

soumyadeepdutta0205-sudo / configurable-cache-memory-subsystem

Configurable Cache Memory Subsystem with Complete RTL-to-GDSII Implementation using OpenROAD.

asic verilog computer-architecture vlsi yosys semiconductor digital-design gdsii cache-memory physical-design openroad rtl-design rtl-to-gdsii

Updated Jul 3, 2026
Verilog

Mummanajagadeesh / inverter-rtl-2-gdsii

Complete ASIC design flow for a Simple Inverter — from RTL (Verilog) to GDSII — using the OpenLane toolchain and the SkyWater 130nm PDK (sky130)

open-source opensource asic rtl abc yosys gdsii openlane gdsii-flow openlane-flow rtl-to-gdsii

Updated Sep 28, 2025
Verilog

aukhalid / evpix_rv32

EVPIX-RV32: 5-Stage Custom RISC-V SoC with Integrated IPU and TinyML Support for Real-Time Edge-Vision AI Acceleration: RTL-to-GDSII Design, Verification, Basys-3 Artix-7 FPGA Prototyping and SkyWater 130-nm CMOS ASIC was implementation

linux makefile systemverilog bash-script verilog-hdl yosys asic-verification openroad asic-design rtl-design fpga-prototyping rtl-verification rtl-to-gdsii sky130-pdk

Updated Aug 17, 2026
SystemVerilog

lanex

AkshatIsWired / lanex

Browser cockpit & IDE for the LibreLane RTL-to-GDS chip flow — run, verify, and explore silicon flows without living in a terminal.

python asic eda vlsi openroad sky130 chip-design eda-tools librelane rtl-to-gdsii

Updated Jul 30, 2026
Python

Zhungg / riscv-alu8-openlane

Signed-off 8-bit RISC-V-style ALU from SystemVerilog RTL to GDSII using OpenLane 2.3.10 and SKY130A.

asic systemverilog alu risc-v static-timing-analysis physical-design openroad openlane sky130 rtl-to-gdsii

Updated Jul 22, 2026
SystemVerilog

Umesh1233229 / Tile_RTL_to_GDSII_28nm_Synopsys

End-to-end RTL to GDSII ASIC physical design implementation at 28nm using Synopsys DC and ICC2 with full timing closure and DRC clean signoff.

asic routing synthesis cts placement vlsi-physical-design pnr cmos digitaldesign icc2 floorplanning designcompiler timing-closure rtl-to-gdsii

Updated Feb 17, 2026

Tavakalmastan / Chiptop-ASIC-PD

ASIC Physical Design of ChipTop using Cadence Innovus | Complete RTL-to-GDSII Flow | Floorplanning | Macro Placement | CTS | Routing | Timing Closure | TCL Automation

vlsi physical-design asic-design timing-closure tcl-script backend-design rtl-to-gdsii

Updated May 17, 2026
Verilog

bangre-16 / UART-RTL-to-GDSII-Implementation

RTL-to-GDSII implementation of an 8-bit UART using Verilog HDL, OpenLane, SKY130A PDK, Yosys, Magic, Netgen, and ModelSim.

magic asic rtl verilog uart vlsi modelsim yosys digital-design netgen gdsii physical-design openlane sky130 rtl-to-gdsii

Updated Jul 1, 2026
Verilog

Vishwajeetsinh-K / RTL2GDS_demux

An RTL-to-GDSII ASIC Flow Project Design, simulate, synthesize, and layout a full 1×8 demux for 8-bit data — all the way from Verilog to GDSII.

asic rtl verilog synthesis hdl vlsi digital-design demux icc2 floorplanning hardware-design clock-tree-synthesis rtl-to-gdsii design-compiler

Updated Jun 4, 2025

KennyLe298 / QSPI-Wishbone

Wishbone QSPI NOR flash controller in Verilog, taken through a full RTL to GDSII flow (Verilator, Icarus, Yosys + sky130, OpenSTA, Innovus)

rtl verilog spi-flash yosys wishbone physical-design qspi innovus rtl-to-gdsii

Updated Jul 16, 2026
Verilog

anlit75 / c4o-core

Underlying EDA toolchain engine for the ChipForAll project.

rtl gds rtl-to-gdsii

Updated Feb 14, 2026
Python

talsania / quartic-rtl2gds

complete walkthrough of the vlsi design process for an equation Y = 4^X development to sta, using synopsys

synopsys synopsys-vcs synopsys-dc synopsys-iccii rtl-to-gdsii synopsys-primetime

Updated Apr 8, 2026
C

adaptableCoder / PWM-OpenLane

RTL-to-GDS exploration of a parameterized PWM controller using OpenLane and SKY130.

rtl-to-gdsii

Updated Jun 27, 2026
SystemVerilog

gou-th / sky130-registered-adder

Full RTL-to-GDSII implementation of an 8-bit registered adder using SkyWater 130nm PDK and open-source EDA tools

verilog vlsi digital-design cocotb physical-design openlane sky130 rtl-to-gdsii

Updated Mar 14, 2026
Verilog

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