Configurable Cache Memory Subsystem with RTL-to-GDSII Implementation

A parameterized cache memory subsystem designed in Verilog HDL and implemented through a complete ASIC design flow from RTL design to GDSII generation using Yosys and OpenROAD.

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Project Overview

This project implements a configurable cache memory subsystem supporting:

• Direct-Mapped Cache Architecture

• Write-Back Policy

• Dirty Bit Management

• 2-Way Set Associative Cache

• Least Recently Used (LRU) Replacement Policy

• Cache Performance Counters

• RTL-to-GDSII Physical Design Flow

The project demonstrates the complete ASIC implementation flow:

RTL-to-GDSII Flow

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Cache Architecture

Architecture

Cache Specifications

Parameter	Value
Address Width	32-bit
Data Width	32-bit
Line Size	4 Words
Cache Organization	Direct-Mapped / 2-Way Set Associative
Write Policy	Write-Back
Replacement Policy	LRU
Technology Node	Nangate45 (45nm)

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Features

✅ Direct-Mapped Cache Implementation

✅ Write-Back Support

✅ Dirty Bit Tracking

✅ Cache Refill Mechanism

✅ LRU-Based Replacement

✅ Performance Counters

✅ Parameterized Verilog Design

✅ Complete RTL-to-GDSII Flow

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Directory Structure

Cache\_Subsystem

│
├── rtl/
├── tb/
├── synthesis/
├── physical\_design/
├── docs/
├── report/
└── README.md

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RTL Modules

Module	Description
cache_top.v	Top-level cache module
cache_controller.v	Cache control FSM
data_array.v	Cache data memory
tag_array.v	Tag memory and valid bits
lru_logic.v	LRU replacement logic
performance_counters.v	Cache statistics
main_memory.v	Behavioral main memory

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Testbenches

Testbench	Description
tb_cache_top.v	Top-level verification
tb_data_array.v	Data array verification
tb_tag_array.v	Tag array verification
tb_main_memory.v	Main memory verification

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Functional Verification Results

Cache Read Miss and Refill

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Cache Read Hit

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Write Hit and Dirty Bit Update

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LRU-Based Cache Replacement

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Cache Performance Counters

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Synthesis Results

RTL Viewer

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Technology Mapping

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Yosys Synthesis Statistics

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Physical Design Flow

The design was synthesized and implemented using:

• Yosys

• OpenROAD

• Nangate45 Standard Cell Library

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Floorplan and Power Distribution Network

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Placement View

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Final Routed Layout

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Physical Design Results

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Final ASIC Implementation Metrics

Parameter	Result
Technology Node	Nangate45 (45 nm)
Final Design Area	101,684 µm²
Core Utilization	18%
Standard Cell Count	189,626
WNS (Worst Negative Slack)	0.00 ns
TNS (Total Negative Slack)	0.00 ns
Timing Closure	Achieved
Physical Design Flow	RTL → Synthesis → Floorplanning → Placement → CTS → Routing → GDSII

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Generated Physical Design Files

File	Description
6_final.def	Final DEF layout
6_final.gds	GDSII layout
6_final.spef	Parasitic extraction
6_final.v	Post-layout netlist

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Tools Used

• Verilog HDL

• ModelSim

• Quartus Prime

• Yosys

• OpenROAD

• Nangate45 Library

• GTKWave

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Future Improvements

• Multi-Level Cache Hierarchy

• Cache Coherency Protocols

• ECC Support

• Non-Blocking Cache

• AXI/AHB Interface Integration

• Cache Prefetching Mechanisms

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Author

Soumyadeep Dutta

B.Tech – VLSI Design

Vellore Institute of Technology, Chennai

GitHub: https://github.com/soumyadeepdutta0205-sudo

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License

This project is released under the MIT License.