icc2

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Umesh1233229 / Tile_RTL_to_GDSII_28nm_Synopsys

End-to-end RTL to GDSII ASIC physical design implementation at 28nm using Synopsys DC and ICC2 with full timing closure and DRC clean signoff.

asic routing synthesis cts placement vlsi-physical-design pnr cmos digitaldesign icc2 floorplanning designcompiler timing-closure rtl-to-gdsii

Updated Feb 17, 2026

rodlie / geticc

Sponsor

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Extract embedded ICC color profiles from files

color image embedded extract file icc color-profile icc2 icc4

Updated Aug 7, 2018
C++

Vishwajeetsinh-K / RTL2GDS_demux

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An RTL-to-GDSII ASIC Flow Project Design, simulate, synthesize, and layout a full 1×8 demux for 8-bit data — all the way from Verilog to GDSII.

asic rtl verilog synthesis hdl vlsi digital-design demux icc2 floorplanning hardware-design clock-tree-synthesis rtl-to-gdsii design-compiler

Updated Jun 4, 2025

3more102 / mips-16-ndm

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Headless IC Compiler II reference-NDM and design-library creation for a MIPS16 ASIC lab - nothing hardcoded, every stage self-verifies before trusting its own pass.

asic tcl eda synopsys physical-design icc2 asic-design mips16 ic-compiler-ii library-creation

Updated Aug 18, 2026
Verilog

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