kria-kv260

Here are 22 public repositories matching this topic...

solomontesema / qcrate

Distributed FPGA instrumentation platform using SystemVerilog, AXI/APB, DMA, PetaLinux, FreeRTOS/OpenAMP, and deterministic timing.

fpga freertos xilinx systemverilog fpga-soc petalinux dma embedded-linux axi rpmsg openamp zynqmp amd-xilinx kria-kv260

Updated Aug 16, 2026
SystemVerilog

VRM21-Studios / FIR-Module-FPGA

Star

A FIR filter for 16-bit stereo PCM audio DSP implemented on an FPGA with fixed-point representation.

fpga verilog xilinx fixed-point fir-filter audio-dsp axi-stream axi-lite kria-kv260

Updated Apr 19, 2026
Verilog

VRM21-Studios / IIR-Biquad-Module-FPGA

Star

Reference RTL implementation of a fixed-point IIR biquad filter with AXI-Stream and AXI-Lite control, validated on FPGA hardware.

fpga verilog xilinx fixed-point audio-dsp iir-filters axi-stream axi-lite biquad-filter kria-kv260

Updated Mar 19, 2026
Verilog

make2explore / AMD-Kria-KR260-Robotics-Starter-Kit

Star

Unboxing and quick overview of AMD Kria KR260 Robotics Starter Kit

machine-learning computer-vision fpga deep-learning robotics hardware-acceleration opencv-python nomachine ros2-humble kria-kr260 kria-kv260

Updated Mar 26, 2026

s59mz / kria-build-system

Star

Automate the creation of a custom Ubuntu-based SD card image for the AMD/Xilinx Kria KV260 board using Docker

kria kria-som ubuntu2204lts kria-kr260 kria-kv260

Updated Sep 15, 2025
Shell

VRM21-Studios / 8x8-Systolic-Array-Module-FPGA

Star

An AXI-native 8x8 systolic array accelerator in Verilog. Features pure dataflow pipelining, Q-format fixed-point arithmetic, and hardware validation on the Kria KV260 FPGA.

fpga verilog xilinx fixed-point axi-stream axi-lite systolic-array kria-kv260

Updated Mar 19, 2026
Verilog

VRM21-Studios / Non-Linear-Distortion-Module-FPGA

Star

A deterministic, fixed-latency tanh non-linear distortion DSP block implemented in Verilog and integrated with AXI-Stream, published as a reference RTL design.

fpga verilog xilinx fixed-point audio-dsp axi-stream axi-lite non-linear-distortions kria-kv260

Updated Mar 19, 2026
Verilog

Devraux / FPGA-Bitconic-Sorting-Algorithm

Star

kria kv260 final project, Authors: L. P., K. P.

sorting fpga pipeline jupyter-notebook verilog sorting-algorithms hdl kria-kv260 bitconic

Updated Oct 11, 2025
Jupyter Notebook

make2explore / Real-Time-Object-Detection-with-KR260

Star

Real-Time Object Detection on the Kria KR260 using a Webcam

machine-learning ai deep-learning object-detection opencv-python yolox kr260 ai-vision kria-kr260 kria-kv260

Updated Apr 3, 2026
Python

ramadan-sokkar-cmd / AES-Project

Star

Hardware/software co-design of pipelined AES-128 using Zynq SoC for IIoT gateways

cryptography fpga zynq aes-128 verilog iiot hw-sw-codesign axi4-lite hardware-accelerator kria-kv260

Updated Jun 20, 2026
Verilog

Baey / bernard_hw_if

Star

ROS 2 node for controlling MD80 actuators and publishing their states. Designed for use on embedded controllers (Kria/ARM64) as part of the BERNARD bipedal robot.

arm64 ros2 ros2-humble ros2-jazzy kria-kv260

Updated Jun 15, 2026
C++

VRM21-Studios / Quadrature-Mirror-Filter-Module-FPGA

Star

RTL reference implementation of a QMF analysis/synthesis filter bank using AXI-Stream, focused on fixed-point DSP and hardware correctness.

fpga verilog xilinx fixed-point fir-filter audio-dsp axi-stream axi-lite quadrature-mirror-filter kria-kv260

Updated Mar 20, 2026
Verilog

THEROHANCHERALA / YOLOv11-Posture-Detection-KV260

Star

YOLOv4 baseline → YOLOv11 optimization for posture detection on Arm Kria KV260 DPU

arm dpu edge-ai posture-detection vitis-ai kria yolov11 kria-kv260 physical-ai

Updated Aug 14, 2026
Python

VRM21-Studios / Audio-Gain-Module-FPGA

Star

Reference RTL implementation of a stereo gain stage, showcasing fixed-point DSP decisions and AXI integration on FPGA.

fpga verilog gain xilinx fixed-point audio-dsp axi-stream axi-lite kria-kv260

Updated Mar 22, 2026
Verilog

VRM21-Studios / Mid-Side-Transform-Module-FPGA

Star

Mid-Side transform RTL (encoder/decoder) in Verilog with AXI-Stream and AXI-Lite control, verified via cycle-accurate simulation on KV260.

fpga verilog xilinx fixed-point audio-dsp axi-stream axi-lite mid-side-encoder mid-side kria-kv260

Updated Mar 19, 2026
Verilog

make2explore / KR260-ROS2-Tutorial

Star

Getting started with ROS2 on AMD's Kria KR260 Robotics Starter Kit

machine-learning computer-vision robotics hardware-acceleration opencv-python dpu ros2-humble kr260 visionai kria-kr260 kria-kv260

Updated Apr 10, 2026
Shell

VRM21-Studios / Simple-Delay-Module-FPGA

Star

AXI4-Stream stereo audio delay implemented on FPGA, using BRAM-based circular buffers and AXI-Lite control.

fpga delay verilog xilinx fixed-point audio-dsp axi-stream axi-lite kria-kv260

Updated Mar 19, 2026
Verilog

VRM21-Studios / Envelope-Follower-Module-FPGA

Star

Deterministic RTL RMS / Peak envelope detector for FPGA audio pipelines. AXI-Stream + AXI-Lite, fixed-point, cycle-accurate, real-time safe.

fpga verilog xilinx fixed-point rms audio-dsp peak-detection axi-stream iir-filter axi-lite envelope-detection kria-kv260

Updated Mar 23, 2026
Verilog

shivanii1111 / Traffic-signal-road-signs-detection-and-classification-yolov5-fpga

Star

pytorch object-detection quantization computer-vision-opencv yolov5 kria-kv260

Updated May 18, 2026
Jupyter Notebook

VRM21-Studios / IIR-1st-Order-Module-FPGA

Star

A first-order IIR filter for 16-bit PCM stereo data implemented on an FPGA with fixed-point representation.

fpga verilog xilinx fixed-point audio-dsp iir-filters axi-stream axi-lite kria-kv260

Updated Mar 22, 2026
Verilog

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