RISC-V Reference SoC Design and Tapeout Program Phase 2 personal documentation
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Feb 19, 2026 - Verilog
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scl180nm
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This repository contains documentation and relevant materials for the RISC-V SoC Tapeout Program, a collaborative initiative between IIT Gandhinagar, VLSI System Design (VSD), and other prominent organizations in the field of semiconductor design.
simulation verification rtl verilog gls synopsys risc-v caravel pdk chip-design functional-simulation scl180nm
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Jan 5, 2026 - Verilog
Designed and implemented a performance-balanced noise-canceling LNA in SCL 180nm CMOS using Cadence Virtuoso, covering CG-CS, Cascode, and Folded-Cascode architectures, RF analysis, full-custom layout, DRC/LVS, PEX, and a custom spiral inductor.
calibre cadence-virtuoso mixed-signal rf-analysis linearity noise-cancellation stability-analysis low-noise-amplifier lna noise-analysis cadence-spectre s-parameter design-rule-check design-for-manufacturability scl180nm full-custom-layout parasitic-extraction layout-vs-schematic custom-spiral-inductor
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Apr 14, 2026
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