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full-custom-layout

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Designed and implemented a low-power hybrid full adder and 4-bit/8-bit array multipliers in GPDK 90nm CMOS using Cadence Virtuoso, including schematic design, full-custom layout, DRC/LVS verification, PEX, and post-layout performance analysis.

  • Updated Oct 21, 2025

Full-custom 8-bit pipelined Vedic multiplier in 90nm CMOS with hierarchical schematic/layout design, DRC/LVS-clean verification, post-layout simulation, and 50 MHz pipelined operation.

  • Updated May 16, 2026

Designed and implemented a performance-balanced noise-canceling LNA in SCL 180nm CMOS using Cadence Virtuoso, covering CG-CS, Cascode, and Folded-Cascode architectures, RF analysis, full-custom layout, DRC/LVS, PEX, and a custom spiral inductor.

  • Updated Apr 14, 2026

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