synopsys-dc

EE577b-Course-Project

Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo

Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.

RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.

This repository contains my BSc graduation project at the Faculty of Engineering, Ain Shams University. The project focuses on implementing the RISC-V core, specifically the CV32E40 ,with a focus on achieving high performance and maximizing frequency through synthesis, place and route (PNR).

My Graduation Project for BSc of Engineering Ain Shams Uni which is ASIC implementation of PULPino SoC based on the cv32e40p (RISCY) core sponserd by ICpedia using Synopsys tools

Full RTL-to-GDSII implementation of a 32-bit RISC Processor. Features Physical Design (P&R), CTS, and Timing Closure using Synopsys DC & Cadence Innovus.

APB based SPI master protocol

complete walkthrough of the vlsi design process for an equation Y = 4^X development to sta, using synopsys

Dockerized container for Synopsys Design Compiler (DC) that can run ANYWHERE.

全國大學校院積體電路設計競賽 實作練習

Logic Synthesis QOR study, the best and worst case for hold and setup

Full VLSI design flow for a 1st-order IIR low-pass filter. It includes VHDL RTL, fixed-point C model, Synopsys DC synthesis with clock gating, and Cadence Innovus place & route. The advanced architecture of the filter applies J-look-ahead, pipelining, and retiming to achieve 581 MHz, a 47% throughput gain over the standard architecture.

Designed a lightweight 3-stage RISC-V processor for anomaly detection applications using Verilog, with RTL verification, synthesis, floorplanning, placement, CTS, routing, and STA using Synopsys VCS, Design Compiler, and ICC2.

This is a basic pipelined RISC-V processor (RV32I) made without a clock (Asycnhronous).

TCL-based heuristic engine for Post-Synthesis Leakage Power Optimization using Synopsys Design Compiler. Implements a Slack-Aware Batch & Revert algorithm.

32-bit RISC-V processor implementing out-of-order execution, register renaming, and precise retirement in SystemVerilog.