synopsys-iccii

Here are 5 public repositories matching this topic...

Siddharth13s / RISC-V_Synthesis_and_Physical_Design

Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo

routing verilog synthesis cts placement tcl-scripts physical-design floorplanning synopsys-dc synopsys-iccii powerplanning

Updated Jul 31, 2024
Verilog

kholoud0 / ASIC-implementation-of-CV32E40P-RISC-V-core-

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This repository contains my BSc graduation project at the Faculty of Engineering, Ain Shams University. The project focuses on implementing the RISC-V core, specifically the CV32E40 ,with a focus on achieving high performance and maximizing frequency through synthesis, place and route (PNR).

asic synthesis implementation synopsys pnr synopsys-dc synopsys-iccii

Updated May 12, 2024
SystemVerilog

mohamedtareq24 / ASIC_implementation_of_PULPino_SoC

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My Graduation Project for BSc of Engineering Ain Shams Uni which is ASIC implementation of PULPino SoC based on the cv32e40p (RISCY) core sponserd by ICpedia using Synopsys tools

asic risc-v pnr synopsys-dc synopsys-iccii

Updated Apr 25, 2024
Verilog

Rakesh-2306 / Ultra-Lightweight-RISC-V-Architecture-for-Anomaly-Detection-in-Healthcare-Application

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Designed a lightweight 3-stage RISC-V processor for anomaly detection applications using Verilog, with RTL verification, synthesis, floorplanning, placement, CTS, routing, and STA using Synopsys VCS, Design Compiler, and ICC2.

routing tcl riscv verilog synthesis risc synopsys risc-v placement tcl-scripts verilog-project static-timing-analysis floorplanning verilog-code synopsys-vcs synopsys-dc synopsys-iccii clock-tree-synthesis

Updated Oct 21, 2025
Verilog

talsania / quartic-rtl2gds

Star

complete walkthrough of the vlsi design process for an equation Y = 4^X development to sta, using synopsys

synopsys synopsys-vcs synopsys-dc synopsys-iccii rtl-to-gdsii synopsys-primetime

Updated Apr 8, 2026
C

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