A SystemVerilog implementation of a 4-bit unsigned array multiplier using structural design. The module computes an 8-bit product from two 4-bit binary inputs by generating partial products and summing them using full adders. Ideal for learning digital design fundamentals and testing with simulators or FPGA synthesis tools.
design digital array verilog systemverilog vlsi testbench system-verilog digital-design computer-organization xilinx-vivado multiplier digital-system-design array-multiplier
-
Updated
May 29, 2025 - SystemVerilog