MATLAB toolbox to read HSPICE generated output files
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Dec 8, 2021 - MATLAB
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post-layout-simulation
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A practical day-by-day journey exploring Digital IC Design using Cadence Virtuoso — from schematics to layouts, DRC/LVS checks, parasitic extraction, and timing analysis.
schematic pex vlsi cadence-virtuoso vlsi-physical-design cmos digital-design custom-layout lvs ic-design drc learning-journal 45nm gdsii-flow post-layout-simulation eda-tools transistor-level-design
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Jul 30, 2025
Designed and implemented a low-power hybrid full adder and 4-bit/8-bit array multipliers in GPDK 90nm CMOS using Cadence Virtuoso, including schematic design, full-custom layout, DRC/LVS verification, PEX, and post-layout performance analysis.
cadence-virtuoso low-power full-adder low-power-comsumption assura array-multiplier post-layout-simulation design-rule-check low-power-design transmission-gate-logic full-custom-layout layout-vs-schematic gpdk90nm
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Oct 21, 2025
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